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Kudos

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Hi all,

I recently came across the need to lock a FPGA ref during some operations to prevent a race condition. While implementing, I naturally thought it would perhaps be simpler to implement using the same mechanism the In Place Element Structure uses to lock the DVR reference. As such, whatever reference wired into the IPES would have the option of being marked as "Blocking".

I have no idea if this is a small change or a huge effort to implement, but I think it can help in managing resources more efficiently - or at least with less steps.

Best,

Cris

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Recursive data types

I've always wondered why this is not possible.

So you can dynamically start a VI. Except when it's not already "running". I quoted running, but the VI itself is not running, it's just on the diagram of a running VI.

To start a VI dynamically, when already "running" we need to make it re-entrant. This is very limiting (see use case in following post).

Technically, there should not be a problem. You can create a new VI, put the sub VI on the diagram and run it.

Why can't we do this by reference???

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If in the middle of building a VI, a user needs to look over something in another project to ensure the 2 programs function together the user clicks File>Open Project this spawns windows explorer where you have to browse to the directory where the project is located at. Since LabVIEW .ini file contains the paths to known projects, the dialog box should populate with the project names and paths for known projects. This allows the user to one-click the project instead of having push down several directories to get there. Of source the user can still browse to another project path not listed in the INI file if the dialog is coded as such. Just a matter of convenience and ease of use

Multi-Board FPGA Generator

To generate a VI or set of VIs with a general driver to get low-end FPGA boards to work with LabView FPGA. Parameters will only come from the users to make this dynamic, this would be the total count of I/Os FPGA type, location of I/O items (eg. buttons) in the FPGA board, etc. It would be a bit of work, but also would pay off at the end. Doing such is no more than an extension of LabView if done well, let's say written in an xml file plus it would be a very powerful tool for researchers, and would generate more sales to use LabView FPGA for more researchers, university students, and engineers who want to test a few things without full initial commitment to NI tools.

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While Loop wait node input

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This NIST site defines a non-integer factorial:

http://www.itl.nist.gov/div898/handbook/pmc/section3/pmc32.htm

The result of the computation is used in statistical process control.

I think that LabVIEW should have its VI's compatible with NIST, and "engineered for process control", seeing how they control processes. The control shouldn't exclusively about operation, but should also have bounds, and quick/effective alerting for out-of-control condition. (OOC).

When I build, I like to test each step. That means that I make a bunch of "debugging" indicators. Some might prefer probes and breakpoints, but I like the "build as you go" and "don't use too many tools". The challenge here is that about 80% of indicators that I make, I have to delete.

I wish there were a version of "diagram disable" that is specified in the block diagram, that worked for the front pane, and left me some tiny asterisk instead of the indicator, that didn't hit program execution times, and that when I configure execution the asterisks can be made to disappear.

This would allow me to revisit my code, to access all of my debugging methods very quickly and intuitively, and to not necessarily change the final layout of the front panel after my debug is done.

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I found a weird configuration in my stuff where a program was not working right because it was clearing out the error code inside a for loop. The for loop was clearing out the error code because it received an empty array from a property node for an array. The property node sent an empty array to the for loop because it received an error on its input.

In the VI where I found this configuration I have an error wire going thru a property node for an array. The values read from the property node are then fed into a for loop and processed. The error wire is fed thru the for loop and then the error is passed back out of the loop in an indexed tunnel and combined with an merge error. When the property node has an error on its input it outputs an empty array. The empty array is then fed into the for loop causing the for loop not to run. The for loop then sends out an empty error wire without the error code that was sent in.

I am attaching a simple VI to demonstrate this behaviour. To see the behaviour toggle the error control on and off.

edit: I forgot to set the default values in the in array on the original attachment

Certified LabVIEW Veteran

This is coercion:

Best practices say it is bad, so how do I fix it? Mindless hunt? Try them all? Sometimes I can't change the upstream data because it is "fresh out of the file-read". Sometimes there is no in-VI upstream to modify outside of the read itself, and that can be challenging with mixed, not explicitly typed data.

suggestions:

I should be able to right-click on the wire an have an option "insert explicit conversion" and have it pick the one that I need, the one it is doing inside the dot, and insert it into the wire just upstream of the conversion dot.
I can configure the outputs representation of many VI's. Can I configure the input representation? That would be explicit.

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A number of elite users consider the VI hierarchy "useless".

The compiler currently makes some assumptions (the detailed particulars of which I have only heard rumors) about the ability of the user to impose a boundary in the block diagram. Whether it is the selection of elements to make into a sub-vi or how frame edges work with memory, there is some assumption there.

Why not remove all the "boundaries" then use graph theory to make better boundaries? I would like to see an "auto-hierarchy" button. When I click it, I would like the tool to remove every artificial boundary, then use graph clustering (reference, toy example) to find actual best boundaries, then impose those.

I would expect a single chain to be in a single "box". I would expect something that starts at a single element, splits into two chains, then re-combines into a single final element to have the head element, the tail element, and two "boxes" which hold the chains. I would expect the box to inform what makes a decent sub-VI during the simplification/splitting of a detailed VI.

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LabVIEW Idea Exchange

In Place Element Structure to lock all types of References

Recursive data types

Add cont. running vi's to Profile Performance and Memory

Allow dynamically running of an already running VI

In Built Stop actor functionality in Actor Framework

Open Projects to populate with list of known projects

Multi-Board FPGA Generator

Connecting two nodes

While Loop wait node input

NIST-compatible non-integer factorial

Development of an Intelligent Debugger

Diagram disable on indicators makes them invisible

Add reentrancy as a source file setting in the build specification

Resetting single channel of NI-9361 when counting edges

niDCPower commit VI should change the range when output is in the off state

Change the for loop to pass out an error if it recieves an error and an empty array as inputs

Call a reentrant VI Front Panle asynchronously from the caller

Certified LabVIEW Veteran

right-click fix coercion (red dot) via autoselected vi inserted upstream

auto-hierarchy via graph clustering