10-Tap 8-Bit camera with one DRAM bank

[volume2]

Hi, 

We have installed NI 1483 adapter + PXIe-7972R. I want to utilize "10-Tap 8-Bit Camera with DRAM.lvproj" example to capture image from camera-link camera (Camera Link Full (10 taps, 85 MHz)). However, our PXIe-7972R only have one DRAM as Fig. 1, and I also cannot select the Socketed CLIP as Fig. 2. Is there any way to modify this program with only one DRAM? The sample code I found on the internet all use two DRAM Banks, thanks.

Best,

Yong

[AlysaOng]

This is really a difficult problem, sorry for not being helpful, I can only provide you with some information reference.
https://forums.ni.com/t5/Machine-Vision/Vision-Dev-Module-image-processing-FPGA/td-p/3753312
1483R for FPGA & 10Tap-8bit question
https://forums.ni.com/t5/Machine-Vision/1483R-for-FPGA-amp-10Tap-8bit-question/td-p/3256024
http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/fpga_dma_fifo_buffer_size/
Cannot Detect Camera Link Camera with my FPGA Frame Grabber
https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019LYaSAM&l=en-MY

[volume2]

Hi, AlysaOng,

Thanks for your reply. 

Now I still try to utilize DMA FIFO for the 80 bit data transfer. And I can detect the camera clock.

However, I cannot acquire the data transfer from camera as following figure. Do you know any hint about this situation?

Best,

Yong

[James_McN · Accepted solution]

HI Volume2,

The answer to your first question is that the DRAM CLIP is not supported on the 797x series. There are some libraries available to achieve a similar thing though in the FlexRIO Libraries palette.

In particular there is an example called Getting Started with External Memory in the example finder (under Hardware Input and Output > FlexRIO > External Memory). This shows the libraries that you can use in action.

I'm not sure about the second question. If these are pulse signals you may not see them on the front panel as they may be too quick to see. If everything is working but these are false I wouldn't worry.

[volume2]

Hi, James Mc

Thanks for your information.

I will study this example code for DRAM control, thanks.

About the second problem, according the follow illustration, I think the frame valid can set to very low (in Hz scale), I just doubt that might be trigger issue. I still try to find the way to acquire the image data via camera control port of camera-link interface. 

http://www.ni.com/tutorial/14244/en/

[manisharma11211]

Thanks for this information. It useful