5122 sampling, decimation & sunchronization

[Gujrat]

Syatem configuration:
1. 8 slot PXI system
2.Five 5122 14-bit digitizer cards
3. one 6602 counter/timer card

Q1. is it possible to synchronize the system to a 10MHz standard frequency (external to the system). is it possible to synchronize the sampling frequency of all the 5122 and clock output of 6602 can be synchronized to the externally supplied 10MHz referecne clock.
Q2. What is decimation in 5122? the datasheet says minimum sampling frequency as 30MSPS then how the digitizer samples at frequencies less than this
Q3. 50ohm cable driving capability of 5122 sampling clock output

[Ayman K]

Hello ,

I would like to answer your question that you posed. Please let me know if you have further questions.

A1: Yes it is possible to synchronize the 5122 cards with an external clock (10MHZ signal). You could either use this external signal as the source of your sample clock or use it as a reference signal. The backplane of the chassis could also serve as a reference signal for your acquisition.

A2: Decimnation is well explained in the NI High Speed Digitizers Help file. I copied and pasted the Sample clock section of the help file. In the case of the 5122, decimnation is allowed with external clocks.

Sample Clock

The sample clock is sent to the ADC of each channel and to the acquisition engine to control the sampling rate of a digitizer. The sample clock sources are as follows.

A3: I would appreciate further details on what is needed here. Are you looking for some specifications about transmission capabilities?

Internal Sample Clock

High-speed digitizers and oscilloscopes have an onboard (internal) clock that controls the sampling rate as well as other timing functionality of the device. In most cases, the onboard oscillator is a Voltage Controlled Crystal Oscillator (VCXO). Typically, an onboard DAC (digital to analog converter) is used to calibrate the VCXO to exactly the desired clock rate. This DAC can also be used to adjust the frequency of the VCXO to phase lock it to a reference clock The maximum sampling rate of a device is usually determined by the speed of the onboard clock. However, other sampling rates can be achieved by two methods; decimation of the data or dividing down the onboard clock.

Decimation Method

In the decimation method, the ADC samples at the rate of the onboard clock and then sends its digital data to a decimator that essentially discards samples at a specific interval to achieve slower effective sampling rates. The valid sampling rates are always an integer divisor of the onboard clock. For example, if the onboard clock is 100 MHz but you want to sample at 25 MS/s, you must use decimation. The decimation method would discard all data except for every fourth datapoint to achieve exactly 1/4 of the maximum sample rate (or onboard clock rate).

Divide Down Clock Method

In the divide down clock method, the onboard clock is sent through a series of clock dividers, and then that clock is sent to the ADC. Typically, the decimation method is preferred over the divide down clock method.

External Sample Clock

Some digitizers and oscilloscopes can accept an external sample clock. This external sample clock is used to replace the onboard clock (the VCXO) for synchronization or to achieve a sampling rate that cannot be specified by using the onboard clock. Some devices can also decimate the external sample clock to achieve a sampling rate that is an integer divisor of the external sample clock. For example, if the external sample clock is 70 MHz, you could decimate the clock by a factor of 2 and achieve a 35 MS/s sampling rate.

Ayman K

[Gujrat]

Thank you very much for your response. I have following understanding from your response. Please clearify..
1. The 5122 in external sampling mode can not sample at a rate more than 30MHz. To get lesser number of samples/sec decimation (it is way of rejecting unwanted samples) can be used. There is no clock (hardware) divider inside 5122.
2. You said the 5122 can be synchronized by an external reference clock (10MHz) from the PXI back panel. You said the internal VCXO can be locked with respect to the external reference frequency. You also said the same external reference can be used as a sampling clock for the 5122. Is threre any addition hardware/software settings to be done if I wish use the external frequency as a reference only or sampling clock? Because as I understand at the same time both the things are not possible.
3. As we know the 5122 minimum sampling frequency as 30MHz then how the ADC would work with a sampling frequency of only 10MHz from the back panel

[Ayman K]

Gujrat,

All your questions are answered in the NI High-Speed Digitizer Help file. You just need to go to the following (Start -> Programs -> National Instruments -> NI Scope -> Documentation -> NI High-Speed Digitizer Help -> Devices -> NI 5122 Overview). Also, refer to the NI 5122 Specifications Document for Specs on the external clock (Start -> Programs -> National Instruments -> NI Scope -> Documentation ->Specifications -> NI 5122)

Here are the answers to your questions:

A1: Actually external clock can sample at a rate between  (30MHz - 105MHz). There is indeed a clock divider inside the 5122 (look at the clocking overview block diagram under Devices -> NI 5122 overview -> Clocking -> NI PXI-5122).

A2: This is also detailed in the clocking section. However, in software you can use the timing scope VIs to specify the source of your reference clock (niSCOPE configure Clock.VI)and also, you could use scope property node to specify the source of your timebase that you want to use for sampling (Sample clock Timebase Source property). You can then export your sample clock or refernce clock using the niSCOPE Export Signal.VI.

A3: This is again what decimation is all about. The 30MHz is when you use external clock but for internal clock you have the 1.526KS/s to 100 MS/s.

Please look at the help file for further details. If you have any questions, please post them here.

Ayman K