5640R FPGA compile error: ERROR:HDLParsers:850

[niton]

hello everybody. I am using 5640R FPGA to build an IF transceiver.

But when I compile the ni5640R template (FPGA).vi in ni5640R template.proj (I diin't change anything in it), I get two errors as below:

ERROR:HDLParsers:850 - "C:/NIFPGA86/srvrTmp/LOCALH~1/NI5640~2/case_23d588e4_frame1_24537948.vhd" Line 163. Formal port B6A8CAB1 does not exist in Entity 'XDataNode'.
ERROR:HDLParsers:850 - "C:/NIFPGA86/srvrTmp/LOCALH~1/NI5640~2/case_23d588e4_frame1_24537948.vhd" Line 237. Formal port B6A8CAB1 does not exist in Entity 'XDataNodeOut'.

Total memory usage is 145632 kilobytes

Number of errors   :    2 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR:Xflow - Program xst returned error code 6. Aborting flow execution...

can anyone help me to solve it ? or, give me some suggestions?

my software information:  LabVIEW 8.6.1, Labview FPGA 8.6.1 , 5640R 1.3.0 , RIO 3.1.0

Thanks!

[Elizabeth_K.]

Hi,

I was able to compile the template fine, although I was using the following versions: LabVIEW 2011, NI-RIO 4.1, NI-5640R 1.6.

Perhaps the issue is somehow related to this Knowledgebase article - KB529DSL03: Why Does Error 6 Occur When Compiling My FPGA Code in Newer LabVIEW Versions?

I would follow the two steps listed there and try to compile again.

1. Right-click the timed loop and select Replace with While Loop.
2. Right-click the newly created while loop and select Replace with Timed Loop.

Regards,

Elizabeth K.

[niton]

HI, Elizabeth K.,

wo have tried your method.

1、Right-click the timed loop and select Replace with While Loop.      （I compiled successfully this time）

2、Right-click the newly created while loop and select Replace with Timed Loop.       （I compiled error this time，there are two errors, just the same as above）

 I try to add a timed loop and complie, I get 4 errors(two couples as above). when I add two  timed loops, I get 6 errors, three couples as above.

By the way, I found that the new-created timed loop is different from the old one.

so the problem should be the timed loop.But I have no idea how to solve it. 

[niton]

Hi,Elizabeth K.,

I have solved the problem. The reason is the version of labview, lavbiew FPGA and RIO driver.

The chinese version of Labview and FPGA may not be compatible with the RIO driver.

now I use english version of Labview 8.6.1, FPGA 8.6.1, RIO 3.1.0. and the errors dispear!

Thank you!