7966R and 5781

[dev_m]

I want to generate a continuous high frequency sine wave signal ( around 20MHz) from 7966R with 5781 as adapter module.I want to use Xilinx core generator .how can i best configure it ? is there any alternative way we can generate a high frequency.Any info is helpful

[Dave.T]

Hey Dev_digilogic, 

I haven't ever ran the 5781 Getting Started.lvproj example(found in the example finder) at 20M, but by default it's set up to output a signal at 1M.  Have you tried to run it at that frequency?  Is there any particular reason you're intersted in using the Xilinx core? 

[dev_m]

i  tried with 20MHz but there are lot of issued regarding  memory overflow because of memory size .i want to use this  high generated frequency to be given as input to  5610 upconverter.

[Dave.T]

Memory overflow in that you need the memory that the waveform is stored on the fpga?   

You could try to use the  Xilinx DDS Compiler, a semi-tutorial on that can be found here.   You'll want to set the dB to somewhere around 80 to get the 14 bits that the 5781 expect.  Then, to convert it from fxp (make sure it's in 14,1 format) you'll use the vi Number to boolean array, then boolean array to number, then to word integer (i16).

I tested the 20 MHz output and it looks good, but I'm assuming you need the resources where the waveform is stored.  

[dev_m]

Thanks for replying.the link provided by you is helpful.I am able to generate a 25MHz from the 5781 adapter using xilinx core DDS compiler .parallely i have checked the output in 5622 digitizer.when i select the full range in DDS the output power level is around 4 dBm.

The settings done in DDS are

system clock 100 MHz.

noise figure: 96 dB

amplitude range.full range

I have feed back the same signal as input to one of the  AI of 5781 adapter.i am observing a huge loss in the signal.

Is it due to 14 bit DAC.( since the output is 16 bit ) if so ? what is the solution to this problem.

waiting for reply.

thanks in advance.

[Dave.T]

Can you post your code or some screenshots so I can get a better understanding of what you're seeing?  

If it's too big to post here you can upload them to  ftp://ftp.ni.com/incoming (you can use windows explorer (windows key + e) as an FTP Client and just paste the link into the bar).  Zip them up and let me know the name of the file. 

I have a 5781 here that I can use to duplicate what you're seeing. 

[dev_m]

hello please find the code for 5781 DDS feedback . it uses two 7966R one for generating the signal and other for reception of signal.please do any necessary corrections required.

waiting for reply

[Dave.T]

hey Dev, 

Two things I see initially are that the Xilinx DDS Compiler is going to be looking for a rising edge, so wiring up a True to the clock will never give it the rising edge it expects.  

Instead, to specifiy the clock on page 2 of 4 of the Xilinx Properties window you'll set the Clock signal name to clk.  I've attached the 3 properties windows, and how I have them configured. 

Next, is the conversion from FXP to i16.  You should try this conversion on the host and see how it performs. You'll find that it doesn't know how to convert the decimal. 

See my second post on a description of how to convert fxp to i16. 

Try these two things and let me know the results.  (I'm playing around with it here as well) 

Thanks! 

[Dave.T]

I said earlier that the AO on the 5781 was 14 bits and that was incorrect, it's actually 16 (you already caught this mistake) so I changed the DDS dB to 96, and then converted it using boolean array method.  

I then put a control on the front panel of the host to adjust the frequency and uploaded the result to 

ftp://ftp.ni.com/outgoing/ 

The file name is DDS Code.zip.   There is the bitfile for the 7966 in there, so you shouldn't have to recompile. You should just have to point the FPGA Open vi to the correct RIO target. 

I only tested the AO using a scope, I've attached a picture of the output. 

[dev_m]

Thanks for replying.I am presently working in 2012 version of labview.so please downconvert it and resend it