9213 and 9217 with CRIO

[QianBath]

Hi all, 

I am using CRIO-9076 with 9205(AI), 9217(RTD) and 9213(TC) module. I am setting up the VI from example vi for both 9217 and 9213, and combining them together.

<-on FPGA

<-on Real Time Target

If I am only using 6 Channels for 9213 and 6 Channels for 9205, the loop rate can be 13ms on average, so it can collect around 76 Samples/sec. Now if I am adding one channel for 9217(RTD), then it cannot collect at the same rate, the loop rate will be around 19ms on average. 

From what I gather, 9213 can gather 100S/s at max rate(high speed mode) if I use 6 channels, so 13ms on average is normal. 9217 can do 2.5ms(high speed mode) if I use 1 channel. 9217 has faster sample rate than 9213, so the loop rate shouldn't slow down by adding in 9217. I am a bit confused here, I hope that someone can give me some thoughts on why this happen and I hope that I explain my problem well. 

[GerdW · Accepted solution]

Hi Qian,

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@QianBath wrote:

I am a bit confused here, I hope that someone can give me some thoughts on why this happen

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You read ALL CHANNELS IN ONE BIG IO NODE! Those channels are basically read one after the other, from top to down.

I recommend to handle the different modules in their own loops - or atleast in their own IO nodes. And of course those IO nodes should run in parallel when you want to achieve max speed…

[QianBath]

Hi GerdW, 

thank you very much for replying. I have no much experience in real time. Thank you, I will give it a try.  

[QianBath]

Hi GerdW, I tried on different IO node, the average loop rate improves quite a lot. Thank you for this. Could you please let me know how to do it on different loop? I have no idea how to make sure they are synchronize. Thank you very much again.

[GerdW · Accepted solution]

Hi Qian,

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@QianBath wrote:

I have no idea how to make sure they are synchronize.

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You use several modules with different sample rates.

You use several frontpanel indicators to transfer data from FPGA to RT host.

And you use one IRQ to signal successful acquisition to your RT host…

So you still can do all 3 steps, even with parallel running loops in the FPGA.

The slowest module should trigger the IRQ, the other modules will be some milliseconds "out of sync" - as they are in your current implementation, too.

[QianBath]

I choose to do like this at the end. Thank you very much for helping me.