Advice on making my project more efficient

[mrtea]

So I have tried this, but it doesn't work exactly as I would expect it to. I have attached what I am at the moment attempting with FIFOs: just trying to get an accurate signal out.

Able to see why?

Cheers

[mrtea]

By not as I would expect, I mean that the output is a square wave regardless of what I try to generate and I am unsure why this is.

This will also continue for a very long time. I have not measured the time this continues for and am unsure why it is happening. Do I instead have to clear it after I complete once cycle? (How do i do this if that is the case).

On a positive, it seems the time base for once cycle is correct. 

[ikaiser]

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@mrtea wrote:

By not as I would expect, I mean that the output is a square wave regardless of what I try to generate and I am unsure why this is.

This will also continue for a very long time.

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Because you are sending your data many times - there is some left over structure that you don't need anymore. In your host.vi, there is the "sending for loop". It checks for the size of your array and then sends the whole(!) array that many times. You needed this before, when you sent every element one by one, but as you can now send them all at once, you can delete the for loop (leave the content).

Apart from that: Your FIFO is configured to be I16, the data you wire to it is DBL. It get's coerced automatically. I don't know what your DBL data looks like, this could alter it in an unexpected way.

The reason for your square wave is probably the following; I remember struggling with this unexpected "feature" during my final university thesis as well. Basically the NI-9263 expects a binary input for its digital to analog converters (DACs). The FPGA I/O node does not convert/coerce values wired to it correctly in this case. Use this formula to convert yourself:

(voltage to output / voltage range) * 2^^ResolutionInBit

Using the values from your project file, it's probably:

(voltage to output / 10) * 65536

See the last sentence in Using FPGA I/O (FPGA Module) - LabVIEW FPGA Module Help for more info, and this older, but more detailed article from June 2010: Converting Voltage Values to Binary Values for the NI 9263/9264/9269 (FPGA Interface) - CompactRIO R....

I made a screenshot of my old code, maybe it is of use for you (different module, therefore I use a different scaling):

[mrtea]

Ok so attached is the updated version of the code. Got rid of the for loop which got rid of the repetition, so now only the one wave is produced as expected. However, the conversion does not seem to have made much of a change.

Making the change, I still see the same square wave. Generating a 1V 1Hz sine wave seems to hit the 10V as a square wave (period 1s as expected).

[mrtea]

Running the fpga side dynamically, you can see that the values straight after coming out of the FIFO are incorrect. I did not encounter this problem without the FIFO when just outputting straight to the analogue pin. Intuitively it feels like there is something wrong with the FIFO I have set up...

Not sure.

[mrtea]

Hi, this is a second post from another thread hoping to get more opinions.

I am sending a single waveform array to a FIFO from a HOST vi and then reading the FIFO on the FPGA side of my code.

The array I am sending does not match the one being received on the FPGA side. It seems whatever array/signal I generate, the outputted waveform is more of a square wave regardless.

Help would be appreciated.

Attached is my project.

Thanks in advance.

[GerdW]

Hi mrtea,

your FIFO is defined to use FXP(±, 16,16) - meaning just integer values!

Maybe you should define a better FXP type? Why not use the FXP type (±, 20, 5) of your AO channel instead?

Also the size of the FIFO is set to 1023 elements. Did you limit your signal generation to create less than 1024 samples to avoid FIFO overflow?

Edit: Please don't ask the same question in several threads. Nobody likes doubleposts here!

[ikaiser]

Yes, that's what I mean with the I16 vs. DBL sentence in my last posting. Did you notive the red Coercion Dots in your host VI?

They show you that some kind of "forcing one numeric format into an other one" is done. This often results in a loss of precision, therefore one should generally get rid of these dots by either converting numeric formats manually (and therefore having control of what exactly happens), or, in your case, find that the FIFO is probably set to the wrong format and fix this (:

The same then happens in your FPGA code, when the I16 value is forwarded to your FXP output (see my previous post)

More information on: Coercion Dots - LabVIEW Help

Hint: Here is where you can change the FIFO data format:

 

You probably want to set it to either SGL/DBL (taking your array into account), or to FXP (when you do the number conversion from DBL to FXP already on the host).