Attempted to access DRAM Address 524288

[MrQuestion]

Thank you for looking into this.

I know how to utilize ModelSim and LabVIEW. I run multiple simulations a day for different projects. The problem is getting ISIM and Modelsim to simulate the DDR memory.  Using block ram (memory elements onboard the FPGA) I have no issues simulating, and even using DDR ram as long as I keep it at one memory partition it works fine sometimes. But it appears that LabVIEW will randomly place the memory partition anywhere it wants in the memory map. Since the simulation tools have limits on memory simulations it's possible to get inconstant simulations because in once case the memory element you were reading was within range, but in the next simulation the memory element is out of range.

It appears that the memory manager in labVIEW FPGA is working much like the memory manager for a PC. Ultimately the developer doesn't care where the data is stored at in memory, just as long as the tool knows where to access it with what ever aliases. This becomes an issue when simulating with tools that have upper limits in combination of labview having memory partitions with a minimum size of 2^17 elements.

The code that I provided will not run in ISIM or modelsim. The tools fail at exactly the same spot when the third memory element is read.

The code that I provided is fairly simple

1.) write to DDR element A

2.) time delay

3.) read the memory from step 1

4.) time delay

5.) write to DDR element B

6.) time delay

7.) read the memory from step 5

8.) time delay

9.) write to DDR element C

10.) time delay

11.) read the memory from step 7

12.) time delay

13.) write to DDR element D

14.) time delay

15.) read the memory from step 13

in both ISIM and Modelsim it fails at around step 11.

If you are running this program without fault in isim. please tell me what version of isim you are running.

Regards,

[Kevin_H.]

Hey MrQuestion,

Just wanted to let you know we're still looking into this. We've been running into some errors that appear unrelated to what you're seeing. I'm going to try to work up (or if you're welcome to work up a simple example and send it to me) a simple testbench which does what you've described. I've been running into strange errors with what you've sent previously.

I'll have an update for you tomorrow.

Regards,

Kevin Horecka | AENIC

[MrQuestion]

When you create a modelsim or isim simulation LabVIEW automatically creates a test bench for you. I am not feeding the simulation any additional input besides what LabVIEW requires. The labview project that I provided is a simple vi that just reads and rights to memory, and doesn't require any external stimulus. Right before the testbench closes i added a simple wait for 4ms. This is so that the testbench doesn't close the simulation early.

If you try creating front panel elements with different names the test bench I provided may not work, because LabVIEW automatically tossed in the front panel VHDL names into the testbench.

So don't use my testbench "as is" expecting that it will work, just use whatever default testbench that LabVIEW creates for you, and add "wait for 4 ms;" to your test bench right before

       PrintHostInterfaceStatus("Closing",HostInterfaceStatus);

The default test bench will always have that line in it to indicate that it is shutting down. by placing a wait statement in there you allow the VI time enough to access the third/second memory element before it stops and crashes the simulation.

This is very important that I simulate this.

[Kevin_H.]

I've been able to get the project you sent over to run in the following version of ISIM without any errors:

 

I didn't see any issues like what you described, but I've attached the directory with all the log files in case you'd like to take a look.

When running in the model sim version you suggested, I get:

# Fatal error at a source-protected location
#

Is this the behavior you're seeing? Do you have access to that ISim version to try it out?

Regards,

Kevin Horecka | AENIC

[MrQuestion]

When running Isim I get the following error

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

at 2412750 ps(1): Note: Running (/tb_nifpgasimulationmodel/).

at 9250 ns(1): Error:

===================================================

Error occurred

Possible reason(s):

LabVIEW FPGA: An error in the LabVIEW FPGA Module has occurred.

Attempted to access DRAM Address 524292

For simulation, the valid DRAM address range is 0 to 524287

Limiting the address in one of the following ways might correct the problem:

Socketed Clip - Random Access: Only access addresses within the valid range.

Socketed Clip - FIFO: Limit the total number of elements written to the FIFO to the maximum range.

FPGA Memory Items: Only access addresses within the valid range and avoid accessing memories allocated to partitions beyond the maximum range.

===================================================

at 9252500 ps(1): Error:

===================================================

Error occurred

Possible reason(s):

LabVIEW FPGA: An error in the LabVIEW FPGA Module has occurred.

Attempted to access DRAM Address 524292

For simulation, the valid DRAM address range is 0 to 524287

Limiting the address in one of the following ways might correct the problem:

Socketed Clip - Random Access: Only access addresses within the valid range.

Socketed Clip - FIFO: Limit the total number of elements written to the FIFO to the maximum range.

FPGA Memory Items: Only access addresses within the valid range and avoid accessing memories allocated to partitions beyond the maximum range.

===================================================

ERROR: Index 524292 out of bound 524287 downto 0.

ERROR: In process LvFpgaSimDram16IntfA.vhd:AccessRamSM

INFO: Simulator is stopped.

ISim>

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

When you modify the tb_NiFpgaSimulationModel.vhd to have the 4ms wait before "        PrintHostInterfaceStatus("Closing",HostInterfaceStatus); " make sure that you rebuild the simulation. ISIM requires that the test bench be created before building the simulation. So the first time you build with ISIM you can't simulate it, because it's in the first build that LabVIEW creates the default tb_NiFpgaSimulationModel.vhd file for you to modify.

 

Notice that the default ISIM only runs about 2.5us. This doesn't allow enough time for labview at access the ram.

In modelsim, you can modify the tb_NiFpgaSimulationModel.vhd file after the simulator is launch, because when you run the do/tcl script it tells modelsim to recompile the testbench.

[Kevin_H.]

Sorry! I had forgotten to add that line in as you had instructed. Although I'm still not getting any errors. I've tried adding "wait for 4 ns;" both before and after the line you've specified. I also tried lengthening that time. I did note that when I added it before, the simulation seemed to lag a hair more at the end, but there were no errors. Any other ideas for ways for me to see what you're seeing?

Thanks for giving such detailed information! I really appreciate it.

Regards,

Kevin Horecka

Applications Engineer

National Instruments

[MrQuestion]

Be sure that you rebuild the simulation export after you modify the test bench.

And be sure that it's for 4 ms not ns. Big difference!

I added in some large time delays in my VI to separate out each action for clearer presentation. This means the Test bench needs to run long enough for the round robin state machine to iterate through each step.

[Kevin_H.]

So nothing I do as far as adding in that line of code (or adding delays in the labview code) seems to create any errors. Maybe I'm missing something still. I have noticed that when I add the line of code to the file you specify and "rebuild" it undoes my changes, but at this point I've tried every combination of adding code and building I could think of. Sorry I'm not having more progress! I've never had to modify the VHD code directly after LabVIEW and before a simulator. Can you think of anything else I might be missing?

Sorry I wrote ns, I'm doing ms.

Are you using the same version of ISIM?

Regards,

Kevin Horecka

Applications Engineer

National Instruments

[MrQuestion]

The test bench should never be modified by labview once it is created, and this is true for everything in the "user" folder of the simulation export.

Are you sure that you are using the same simulation export every time? Once you modify the test bench be sure that you rebuild the same simulation export related to the test bench that you just modified.

If labview is overwriting the testbench when you compile then there is something really horribly wrong. 

We both have the same version of isim.

I'm think the reason that you are not seeing any issues is because you are not running the simulation long enough for the VI to access the memory elements. The test bench is shutting you down.

In a previous image that I attached the simulation only ran for about 2500ns. That is with the default test bench with modelsim. So, if it says "R'u'n'n'i'n'g" for only 2500ns, then you will never see this issue in isim.

[Kevin_H.]

If you just sent me the build output from LabVIEW would I be able to replace my files and run them in simulation? Can you just send me that entire directory in a zip? We'll get this figured out! The Rebuild is overwritting the files again, the Build just says there's no changes and makes no modifications to files.

Kevin Horecka | AENIC