BRAM Parallel read

[Terry_ALE · Accepted solution]

Yes but they have to be separate BRAM configurations.

[Intaris · Accepted solution]

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@ahmalk71 wrote:

With other words I can read multiple BRAMS in parallel if insaide a SCTL? Or did I misunderstood your "Of course if you have multiple BRAMS, you can read each one simultaneously. In SCTL at least."?

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Correct.

[ahmalk71]

Well this is what I want to do, I create 32 memory Items in the project and drag them to the my FPGA VI. But I i don't create all of them manually, what I do is to create one and copay paste it into the project. I believe this is same as configuring each one manually. 

[Terry_ALE]

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@ahmalk71 wrote:

Well this is what I want to do, I create 32 memory Items in the project and drag them to the my FPGA VI. But I i don't create all of them manually, what I do is to create one and copay paste it into the project. I believe this is same as configuring each one manually. 

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Yes, you can copy and paste in the project.  If you need to make a change, you need to go into all 32 of them.

I recommend using VI defined memory items where it gets configured in the VI and that VI is used over and over.  So a change in config means only one location needs to be changed.

[ahmalk71]

Never used that before, I'll look into it. thank you for your help. 🙂

[Intaris]

I'm with Terry.

VI-instantiated FPGA resources are definitely preferable to project-defined items.

[ahmalk71]

I agree, If you know how to do it 😞 Right now I struggling to figure out how to do this. If I create one VI-defined memory item I need to reference that to 32 reentrant VIS with write and 32 reentrant VI with read (two different loop for read and write). But how can I be sure that the VI I'm reading from is the one I wrote to. I mean If I write the channel 5 sample into the one of my 32 write vis how can I be sure that the right VI is used to read channel 5. I tried to find an example, but the only thing I find is how to configure one memory.

I looked at the description of VI-defined memory configuration nod. It says the following:

If you use a VI-defined memory item in a reentrant FPGA VI, LabVIEW creates a separate copy of the memory item for each instance of the VI to avoid resource conflicts.

Dose that mean that I should have the configuration node inside the reentrant VI? If so how on earth should I link that to the reader VIs.

[Terry_ALE]

Best to take a step back and think about the whole thing more abstractly.  Whatever manages the BRAM should all be in one VI.  That extra time up front will save you time with code that is hard to manage.

[ahmalk71]

Thats gonna be a tricky challange 🙂

[Intaris]

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@ahmalk71 wrote:

I agree, If you know how to do it 😞 Right now I struggling to figure out how to do this. If I create one VI-defined memory item I need to reference that to 32 reentrant VIS with write and 32 reentrant VI with read (two different loop for read and write). But how can I be sure that the VI I'm reading from is the one I wrote to. I mean If I write the channel 5 sample into the one of my 32 write vis how can I be sure that the right VI is used to read channel 5. I tried to find an example, but the only thing I find is how to configure one memory.

I looked at the description of VI-defined memory configuration nod. It says the following:

If you use a VI-defined memory item in a reentrant FPGA VI, LabVIEW creates a separate copy of the memory item for each instance of the VI to avoid resource conflicts.

Dose that mean that I should have the configuration node inside the reentrant VI? If so how on earth should I link that to the reader VIs.

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Quite simple, you pass wires around. YOu can configure a sub-VI connector pane to be a BRAM FPGA reference of a specific datatype. You can then configure the BRAM in yourr top-level VI and pass it into 32 sub-VI instances....