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Bit packing and unpacking

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@rolfk wrote:

Arrays of booleans are definitely suboptimal even on other platforms than FPGA. There is a small chance that the FPGA platform does some specific optimization under the hood to convert boolean arrays of limited size into integers anyways as that is more efficient to implement into hardware but on non-FPGA platforms each boolean always uses up an entire byte and so an array of 32 booleans uses 32 bytes, needs to be dynamically allocated and deallocated and incurs extra overhead when referencing the bits. If you use integers with boolean arithmetic instead you keep the code the same on all LabVIEW platforms and also get the most performant solution on each platform too!


I am almost certain that the boolean array in an FPGA compiles down to individual lines and gates.  So a boolean array with 8 items will use 8 lines/gates.  So it should come out to the same fabric size as the U8.  Though, I am willing to bet the U8 can use the DSPs instead of LUTs and other fabric.  So that is another risk on the FPGA side.


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