Block RAM in PXIE-7965R

[nmbernardo]

I am using memory item in my fpga code.  However, it utilizes a lot of fpga slices eventhough I selected block memory implementation of the memory item. I though It should use block RAM instead of other fpga resources. The number of total slices increases as I increase the number of data in the memory item. It seems that it is using fpga slices. I attached the LabVIEW FPGA project and the FPGA VI with this post. The FPGA target is PXIe-7965R. Thank you for your help

[david1147]

Does the slice increase come in proportion to your memory usage? Besides, quite a lot slices are occupied even if you compile an empty VI. Have you cut that number from your benchmark?

[nmbernardo]

I haven't discarded the number of slices used when compiling an empty VI. I tried compiling an empty VI and it already used up around 9% of total slices. Is it really normal to have this much total slices utilization when compiling FPGA VIs in LabVIEW? >_<

[david1147 · Accepted solution]

LabVIEW FPGA needs to put some logic on the fpga to take care of the communication between the chip and your host, such as control/indicator communication, dma channel setup logic. While LabVIEW FPGA provides you with the ease of use experience, there is some cost to pay. For most of the times, this cost is acceptable compared to your real application.