LabVIEW
Building a trivial VI for FPGA takes several minutes - why, and can it be made faster?
Solved!
I'm using NI PXEe-7820R and LabVIEW 21.0.1f1. My desktop workstation has 6-core Intel i7-8850H and 16 GB of memory.
When I start a new FPGA project and create a simple test VI, which only sets one digital output to true, building it takes 4:26 with the default settings and 3:56 if I enable "Reduce compilation time" in Xilinx compiler options.
In the working directory of the build, there is a large number of VHDL files (see screenshot below) - to be exact, 174 of them. Are they causing the long compilation time? Are all of them actually needed for the project - can I build the VI without them?
If the extra VHDL files are not the culprit, what would then be the reason for the long build time?
Thanks for the help!
VHDL compilation is a complex matter and your compilation times for a simple routine are very common for that. There are a number of reasons:
LabVIEW is abstracting away a lot of complexity in programming FPGA hardware. This comes at some cost as it creates quite a bit of boilerplate framework code to allow to easily interface with the NI-RIO driver that sits below of all the RIO functions you can seamlessly access through the FPGA method and property nodes, when trying to communicate with your FPGA program through registers (front panel controls), interrupts and FIFOs. LabVIEW might be able to strip some of this a bit more for very trivial FPGA programs than it currently does, but that makes everything also more complicated and error prone. Considering that most users who go to the length of buying a not inexpensive FPGA hardware and the according LabVIEW Realtime and FPGA licenses to do something with it, are not really interested to just build a LED flickerer except maybe for their first test example to see how creating such an FPGA program works, it does not make a lot of sense to spend huge amounts of effort and resources to try to squeeze out a minute more from such a compilation. Fact is that VHDL compilation is extremely slow if you compare it with a typical LabVIEW VI compilation even if you work directly with VHDL files and invoke the VHDL compiler from the command line. LabVIEW needs a fraction of a second to compile a VI, a VHDL compiler needs typically many seconds for each individual VHDL file and then even more time to combine the resulting design into a whole, place the gates, and route and optimize the actual logic map to the final binary bitmap file.
So yes 4 minutes is not very strange and about what you can expect to have to wait at least. There are a few things you can do to manage this better. If you have an active SSP with your LabVIEW FPGA license, you also have the right to use the NI compiler farm that they operate in the cloud. This compiler farm lets you offload the entire Xilinx compilation to it directly from within the LabVIEW build dialog. LabVIEW still needs to go through the step of exporting the VHDL code from the VI, which does take some time too but after that you can happily go on and keep programming your next improvement or a different routine until the compiler farm server sends you a message that the compile is finished. On my not that old laptop with 16GB of memory, I actually notice that the compilation in the compile farm is usually faster than if I would do it locally on my own computer.
If your computer is resource constrained, then upgrade its hardware. A fast CPU helps but more memory helps always even more. 16GB of memory is the absolute minimum you should have for the Xilinx compiler toolchain. Anything below that will simply make your compile times explode exponentially. Anything more you can throw at it will help.
@okahilak wrote:
I'm using NI PXEe-7820R and LabVIEW 21.0.1f1. My desktop workstation has 6-core Intel i7-8850H and 16 GB of memory.
When I start a new FPGA project and create a simple test VI, which only sets one digital output to true, building it takes 4:26 with the default settings and 3:56 if I enable "Reduce compilation time" in Xilinx compiler options.
In the working directory of the build, there is a large number of VHDL files (see screenshot below) - to be exact, 174 of them. Are they causing the long compilation time? Are all of them actually needed for the project - can I build the VI without them?
If the extra VHDL files are not the culprit, what would then be the reason for the long build time?
Thanks for the help!
Ever work with FPGAs?
It is not software.
Lots of big differences.
Regarding compile time see
https://www.quora.com/Why-does-FPGA-synthesis-take-so-long-to-execute
