CRIO and FPGA mode chassis interface - Best design approach

[Mauritius]

Hello super NI FORUM.

Need some info how to build at stable HIL (Hw In the Loop) system using the cRIO.

Problem is that the system feels a bit unstable..

My system has this scenario:

NI Host on XP computer (showing model state and various inputs, toggle/change model parameters in FPGA and Realtim vi)

Realtime VI on 9082 + FPGA VI (Realtime running slow model changes and calculations, and FPGA is runnig highspeed calcs)

Extend I/O through EtherCAT to 9144. (To add more I/O to the system, it is OK that they are not realtime)

Would like some ideas how to build this system, so that it is easy to change and add variables.

Eg. how to pass data down to and from realtime VI and FPGA VI.

As the system is now, it is a combination of user-defined variables (UDV) and network variables. Some UDV in FPGA is written from Realtime VI and some from Host VI on XP computer. Some variables is passed down to FPGA from Host VI through Network shared variables to the Realtime VI and fed into FPGA.vi through "Read/write Control Function" in Realtime Vi and in simmilar way fed back up to the host.

It is "a bit" messy code, but there has been many developer during the code lifetime.. :-S

Any input to do this the right NI way? 🙂

I can maybe create a sketch for the system to clarify, if someone is interrested?

[A.Rohde]

Hi Mauritius

What do you mean by your system is unstable?

Are the loop rates on the FPGA unstable? If so, are you using DMA transfers other other ressources with a timeout of "-1"?

Are your loop rates on the real-time host unstable? If so, have you split your RT code in a deterministic and a non-deterministic part? Are you having any non-deterministic operations in your deterministic loop?

My best recommendations for you in regaring to transfer must be.

To transfer data between the PC host and the cRIO controller you can use Network Shared Variables for communication where you don't need every value. The network shared variables will not buffer you data and cannot garantee that the cRIO reads all of the values and only read them once. So they are good for instance on sending data that is shown in an indicator (not graph), or to send a boolean value like a stop button, it doesn't make a big difference if you loose one iteration for the stop value, then it will just stop the next time. If you on the other hand need all values, you should consider using the network streams functions instead.

The same goes on between the RT and the FPGA. For communication where you don't need every value and you are fine with just reading the latest value you can use the Read/Write control nodes. If you need to send the exact data instead I would recommend you to use the DMA FIFO's.

You can read much more about the communication between the different targets in the NI CompactRIO Developers guide found here: http://www.ni.com/compactriodevguide/

I'd recommend you to monitor your loop rates like described here for the FPGA (same can be used on RT and Windows with their appropriate timing functions)

http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgahelp/meas_while_loop_execution_rate/ 

If you need more concrete advise you need to be much more specific about what you mean by unstable and include snippets of your code. 

Best Regards

Anders Rohde

Applications Engineer

National Instruments Denmark