Can I acquire singals of frequency greater than 40MHz using 7831-R FPGA module without loss of data? Say 100 Mhz signal

[LabWiz]

Can I acquire singals of frequency greater than 40MHz using 7831-R FPGA module without loss of data? Say 100 Mhz signal.
LabWiz

[FrankyD]

I think the FPGA analog input A to D is limited to 200kHz.

[Christian_L]

The analog inputs are limited to about 230 kHz. The digital inputs can acquire data in a single clock cycle if the arbitration is disabled. This means you can theoretically read a digital line on every clock cycle of the FPGA (40 MHz, or even 80 or 120 MHz). However, by placing the digital read inside of a loop, you add the loop overhead to the read cycle and the maximum speed at which you can read is about 10 MHz for a 40 MHz FPGA clock. If you compile your VI for a faster FPGA clock (80 or 120 MHz), the maximum loop rate will increase accordingly. Whether you can compile your VI for one of these faster clock rates will depend on the complexity of the code in your VI.

If you add more code to your loop, then the loop rate and the speed at which the dig
ital input is read is reduced. If you do have a number of functions that need to be performed inside of the loop, you can often improve the loop rate by using shift registers and putting some of the functions inside the loop into parallel execution flow. This methodology is commonly called 'pipelining'.

Christian L
NI Consulting Services