Hi,
I am trying to implement UART in FPGA. I am using Labview 10 and 7854R FPGA.
UART is implemented correctly. It can send and receive the data correctly.
But it can send or recieve data at some rates multiple of 40 Mhz only. I can not send data at standard baudrate like 115200 (115.2K). I can send data at the rate of 100K instead.
So, to achieve standard rates I decided to use derived clock of 36.92.. (12/13) Mhz. but it can be used only with SCTL (single cycle timed loop). My code do not run in SCTL. so, i had to use simple while loop. If while loop can use derived clock then problem is solved. Question is How ? Can any one guide ?
Regards,
Hitesh Dhola
