Changing amplitude of TTL pulse

[aerochem]

Hi,
  I am trying to devise an FPGA program that generates a sequence of TTL pulses that will serve as triggers for laser firing.  ALthough the manual says the pulse amplitude can be 3.5V or 5V, it does not say how to change the amplitude.  Currently the amplitude we get out (read on oscilloscope) is 3.5V. How can i change it to be 5V?
 Thanks

[dpacaba]

Hello aerochem:

I assume that you are using LabVIEW FPGA module...
Could you please inform us what hardware do you have?

[aerochem]

Yes the hardware we have is a
PCI 7831R Device in a SCB-68 housing
Software: Labview 7.1
FPGA Module 1.1

Thanks

[AnalogKid2DigitalMan]

From section 2-15 of the manual:

The DIO lines on the NI 783xR are TTL-compatible. When configured as
inputs, they can receive signals from 5 V TTL, 3.3 V LVTTL, 5 V CMOS,
and 3.3 V LVCMOS devices. When configured as outputs, they can send
signals to 5 V TTL, 3.3 V LVTTL, and 3.3 V LVCMOS devices. Because
the digital outputs provide a nominal output swing of 0 to 3.3 V
(3.3 V TTL), the DIO lines cannot drive 5 V CMOS logic levels.
To interface to 5 V CMOS devices, you must provide an external pull-up
resistor to 5 V. This resistor pulls up the 3.3 V digital output from the
NI 783xR to 5 V CMOS logic levels. Refer to Appendix A, Specifications,
for detailed DIO specifications.