Clip to host data transfer.

[kimduil]

I want to send data from a VHDL clip in FPGA to host (PXI system with NI7852R). The clip is included in a single cycle timed loop. Data (U32) is accompanied by a pair of handshake signals (Write/Acknowledge). I know that I have to use a Target to Host FIFO but I don't know how to interface the signals from clip to the write part of the FIFO.

[Sang-yun]

Hi kimduil,

If you want to use CLIP, you should Import VHDL code to communicate with FPGA VI.

To add CLIP to an FPGA target, you must provide IP in the form of VHDL code to compile into the FPGA target.

Please see below link for more information.

http://zone.ni.com/devzone/cda/tut/p/id/7444

ps. If you are Korean, you can see it easily with below link as translated into Korean.

http://zone.ni.com/devzone/cda/tut/p/id/11824#toc2

Regards,