Communication Protocol between PC and FPGA

[FabFet]

Hi dear Expert,

I want to synchronise communication between a Vi on my PC and a VI located in the FPGA of myRio 1900. In fact I want to read data from a file on the PC, write the data from the file to  DMA FIFO 1. On the FPGA, I want to read the DMA FIFO 1 and save the data in Memory. This is required because the processing algorythm need all the data. After saving the all the data to memory, I want to Read them back, process them and write them back to the memory. Once the processing is done, I want to read the processed data from the memory and write them to DMA FIFO 2. At the end of last operation on the FPGA, I want to inform the VI on the PC so that it can start reading the processed data and storing them and the cycle re-begins.

I have illustrated it as follow

I am a new programmer and I would be glad to take advice about how to design a better communication protocol and if my design is acceptable, what will be the best way to implement it. Thank you in advance

[GerdW · Accepted solution]

Hi FabFet,

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@FabFet wrote:

I am a new programmer and I would be glad to take advice about how to design a better communication protocol and if my design is acceptable, what will be the best way to implement it.

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LabVIEW RT+FPGA comes with lots of example VIs and example projects. In those example projects it is explained how to transfer data between host computer, RT target and FPGA inside RT target.

Have you studied those examples?

Which problems do you encounter?

Where are you stuck?

[johntrich1971 · Accepted solution]

Do you understand what a FIFO is? Based on the information in this post and your other post that you're trying to solve a problem that doesn't exist. There will only be data on the FIFO when you put it there. When you take the data off of the FIFO and then loop back you will get the next data point when it becomes available. As GerdW said you should check out the examples and then come back here with specific questions that you might have.

[Bob_Schor · Accepted solution]

It sounds like you do not understand that there are three processors involved in transferring data from FPGA to a PC.  One processor is in the PC.  The second processor is a "Real-Time Target", a stand-alone "computer" running a Real-Time Operating System (usually NI Real-Time Linux), and an FPGA Chip that is part of the Real-Time Target.  The PC typically communicates with the RT Target using TCP/IP (though LabVIEW can make this almost "invisible", particularly during Software Development).  The RT Target and its embedded FPGA Chip have protocols for sending Data back and forth between them, including a FIFO mechanism for moving large quantities between Target memory and the (relatively-limited) FPGA "memory".

Bob Schor

[FabFet]

Hi GerdW,

Thank you a lot for your reply. In the past few days I looked at some NI examples and watched some YouTube videos. After that I was able to implement communication between a VI on the PC and a VI on the FPGA of NI myRio 1900 using FIFO DMA.

Note: the FPGA Target is in "simulation" mode and I will later move the VI from the PC to the Realtime Target when I run the FPGA in "normal" mode

[FabFet]

Hi John,

Thank you for the clarification. It took me some time to understand the way a FIFO works. Now that I have tested data transfer between PC and FPGA (Simulation Mode), I have noticed I do not really any synchronization mechanism to make it work. 

[FabFet]

Hi Bob,

Thank a lot for your more than detailed response. That really completes my knowledge and clears the doubts I had.