Compilation failed due to timing violations, Getting Xflow error and resources over use.

[lv1]

Hi,

I am extensively using Fixed point math library functions which i have downloaded from NI website in my FPGA application.I am getting following errors while compiling the code.

I would like to know is there any limitations in using fixed point functions?

I am configuring all funtions as a 64 bit word length and 32 bit integer length in cofig parameter set up and all are outside the timed loop.

Apart from below error it is occupieng LUT's 300% in one simple VI (mathematical calculations using fixed point functions).

So i would like to know is there any way to optimize the code?.

Status: Compilation failed due to timing violations.

The compile process reported a timing violation.

Suggestions for eliminating the problem:
  * For Timed Loops with timing violations
      - Reduce long arithmetic/combinatorial paths
      - Use pipelining within Timed Loops
      - Reduce the number of nested case structures
  * Reduce clock rates if possible
  * Recompile

Refer to the LabVIEW Help for more information about resolving compilation errors. Click the Help button to display the LabVIEW Help.

Compilation Summary
-------------------

Device Utilization Summary:
   Number of BUFGMUXs                        2 out of 16     12%
   Number of External IOBs                 214 out of 484    44%
      Number of LOCed IOBs                 214 out of 214   100%
   Number of MULT18X18s                     69 out of 96     71%
   Number of SLICEs                       4387 out of 14336  30%

Clock Rates: (Requested rates are adjusted for jitter and accuracy)
  Base clock: 40 MHz Onboard Clock
      Requested Rate:      40.408938MHz
      Achieved Rate:       36.974044MHz    <<<=== Timing Violation

[tst]

As far as I know, this library is only a demo and you should not use it in any real applications, since it's not a completed product. I wouldn't be surprised if the license for it doesn't even allow using it commercially. You can find more details (and possibly an answer to your question) here.

[griffindore]

The Fixed Point Library is certainly not a demo, and we encourage you to use it extensively. The timing violation generally corresponds to code in the Single-Cycle Timed Loop (SCTL) taking too long to execute. When you increase the number of bits in the fixed point numbers, the computations become more complex and can begin to take too long to execute in a SCTL. It also requires more combinational logic which most likely accouts for the 300% LUTs. Do you need 64 bit word length for the fixed point numbers? I'd suggest decreasing the number of bits for your fixed point numbers and see if that corrects the issue.

[lv1]

Hi Mike,

Thanks for your prompt response.

I changed 64 bit word length to suitable word length,it sounds good.But as I increase the code(fixed point functions) getting Xflow error.

Is there any other way to optimize the code?

Regards

Ravi

[tst]

---

lion-o wrote:
The Fixed Point Library is certainly not a demo, and we encourage you to use it extensively.

---

Really? "Demo" is perhaps too strong a word, but the NI Labs page says that the toolkits there "aren't quite ready for release" and are "experimental prototype"s. My understanding was that they work, but are only meant to show potential future products and get feedback on them. If this is not the case, perhaps the wording needs to be changed.

I know I wouldn't want to be using something throughout my code and then find out that it is not supported when the next LV version came out because it was only a prototype. Can you promise support into the future for these? If you can't, that should be clearly stated.

[griffindore]

Hi lv1,

You have to keep in mind that every time you add a fixed point function, you are increasing the number of combinatorial logic you are using. I would refer to the following KnowledgeBase on how to optimize FPGA resources.

How Can I Optimize/Reduce FPGA Resource Usage?