Compile FPGA Hangs on 7852R Board

[otheredward]

Hello,

I am working on a quick program to count edges from an input signal. The FPGA program I'm trying to compile is shown in the attached PNG file. When I try and compile the program the compiler gets to a spot, shown in the other attached PNG file, and hangs. Every example FPGA I've seen thus far uses memory items or FIFO for storing data but I've tried using an array. Could this be related? Are arrays supported in FPGA or should I not use them. With the FIFOs you pick if its in block memory, LUTs, or gates. If you use an array as I have how do you specify where the array is on the FPGA?

Thanks,

Edward

[otheredward]

Hello, had a second to look into this a little more. I made a simpler program to test the problem as shown in the attached screen shot. I've found if I set the dimension of the fixed array being wired into the single cycle timed loop's shift register at ten elements everything is fine. The program compiles without a problem. If I set the size of that array at say 8199 elements it hangs on compiling suggesting the problem is related to the array size. Which brings up an interesting point. How big can I make an array in FPGA with the 7852R board? Clearly ten works but what's the upper limit? Additionally how is the FPGA storing the array, does it default to LUTs, block memory, or gates? I haven't found any documentation on this, can someone tell me were to?

Thanks,

Ed

[_enigma_]

Hi Ed,

FPGAs are good at processing simple tasks and logic at high speeds, but can get bogged down quickly when thrown a ton of array data to store & process.  Arrays consume significant space on the FPGA because each bit in the array uses a flip-flop on the FPGA.  On top of this certain array functions can make things worse, such as Index Array which consumes logic resources in proportion to the size of the array and may not execute within a single clock cycle.

However there is no need to fear, there is a solution: Replace arrays with Memory Items or FIFOs and change your logic operation to operate element wise.  This will free up your logic resources and speed operation.  The best references I have for this topic are in the LabVIEW FPGA Module Help linked below.

Limiting the Number of Front Panel Objects in FPGA VIs (FPGA Module)

Storing Data on an FPGA Target (FPGA Module)

Transferring Data between Devices or Structures Using FIFOs (FPGA Module)

Regards,

Alexander M

Applications Engineer

National Instruments