Configuration of RTSI_ref_clk for FPGA compilation

[raj_345]

Hi All,

 I have a target VI which has a HDL Node inside it. I configured the RTSI_ref_clk using the "Compile for a single frequency" option and
generated the bitfile and the functionality of the bit file is as expected.
 Now, I want to generate a bitfile which can work for a range of frequencies. For this, I configured the RTSI_ref_clk using the
"Compile for a range of frequencies" option. The generic variable named Clock Frequency of the HDL Node is configured to a fixed frequency irrespective
of the range provided. And when CheckSyntax is done, the following error is displayed.

ERROR:HDLParsers:414 - "C:/DOCUME~1/Test-01/LOCALS~1/Temp/WBM_Tx.vhd" Line 10. The integer value of 4293967296 is greater than integer'high

Can you provide any help to resolve this issue. Please its urgent

Regards,
Raj

[raj_345]

Hi all,

   Did anyone tried using the "Compile for range of frequencies" option in RTSI_ref_clk properties window?(Under Clocks of FPGA Target - PXIe-5641R)

[sumit.sen]

Can you please specify about the Software environment and the corresponding versions you are working with?

[raj_345]

Labview2009 with FPGA Module.

PXIe-5641R IF RIO Transceiver - H/W