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Control FPGA state machine from the host

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Again thank you , i put the "retrieve data" from DRAM to the DMA , and now able to read back the data at host. (just for self test).

I need to read the data from the dram to a fifo , but not the whole data , but for example 100 bytes , and send from the fifo outside.

i thought about a counter and multiplier which will increase by 1 one each time i've sent 100 bytes , till i achieved the final address , i think that thats not so good idea because i need to perform multiplication at the target side. Any suggestion for a better way ?

 

Thank you.

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