Control values with case structure in FPGA

[RRI_user]

I am using NI PXIe-1062Q Chasis (connected to a Dell workstation Precision 1700) with the following modules :

1. NI PXIe-8381

2. NI PXI 7851 R

3. NI PXIe-6738

4. NI PXIe-6535

In my workstation, I have plugged in the PCIe-8381 module for connecting NI PXIe-8381 to the computer into a PCI-E Gen 3 x16 slot. I want to execute a sequence of operations from NI PXI 7851 R FPGA card using an FPGA VI controlled from a Non-FPGA Host VI. For this, I write the operations inside a case structure in my FPGA VI. The user will give the sequence of operations by simply typing the array of numeric values corresponding to various operations of the case structure in the order he/she wants. This array is transferred from the Host to FPGA VI by a DMA FIFO. Now here is my question :

Q.1. Suppose I have an FPGA Wait function (with a control value passed from Host VI) as a particular case of the case structure in FPGA VI. I want the user to be able to specify different control values for the same Wait function case of the FPGA VI i.e. suppose the wait function case is no. "2". So In my FIFO whenever I say "2" I should also tell the control value for this particular occurrence of the "case 2". Next time when again "2" occurs in the FIFO it will have its own control value which might be different from that of earlier "2". Is there a simple way of passing the control values each time the particular case is called from the Host? Right now I can specify one wait time control value in the Host which passes to FPGA VI say 1 μs. If I want to wait for 100 μs I have to type "2" 100 times in FIFO. But this is not user-friendly and might not be a solution always. Here it works because time simply adds.

This method would help when I scale the FPGA VI later adding several cases some of which might have control values coming from Host. Whenever the Host calls these particular cases, it should also tell all the control values required by a particular case for this single occurrence. Later on, if this case is called again in the FIFO, a fresh set of control values will be supplied by the Host VI.

I am attaching my Host and FPGA VIs and their screen-shots. I tried to switch ON a TTL signal in one channel of Connector 0 of 7851R. After some wait time  (1 μs), I switch off the TTL signal in the channel (FIFO array sequence from the host is: 1,2,3). I see a nice TTL pulse on my oscilloscope but the above issue remains to be resolved.Top_level_Non_FPGA_VI_using_FPGA_FIFO_VI

FPGA_VI_using_FIFO

[Terry_ALE]

See below the ways of interfacing Host and FPGA VIs

http://zone.ni.com/reference/en-XX/help/371599M-01/lvfpgaconcepts/fpga_host_comm/

Reading and writing from/to controls/indicators also is not deterministic.  To be deterministic you will need to use a DMA-FIFO.

[RRI_user]

Sorry for not replying for a long time. I was trying to figure out a solution. Right now I have thought a highly unconventional way of solving it. I use a DMA FIFO of U64 data type. Now every element of this FIFO requires 64 bits. What I do is partition these 64 bits to send the information from Host to FPGA regarding control values. Say I dedicate the first 10 bits to determination of case number. So I can only have about 1000 cases but that is sufficient for all my future purposes. The remaining 54 bits I will partition as per the particular case of the case structure. An example :

Suppose I want to call case number 2 which is the wait case but with different wait times for each call say first 1 µs and then 2 µs. So first ten bits represent the case number (in binary) and we have 0000000010. Now the remaining 54 bits will tell the values for all controls (here only one). For 1 µs we have "53 0s and then 1" and for 2 µs we have "52 0s and then 10". The total 64 bit binary numbers look like :

For 1 µs wait : 0000000010000000000000000000000000000000000000000000000000000001

For 2 µs wait : 0000000010000000000000000000000000000000000000000000000000000010

These two numbers I convert to decimal and supply to FPGA via DMA FIFO. So the numbers look like :

For 1 µs wait : 36028797018963969

For 2 µs wait : 36028797018963970

Now when FPGA receives these numbers, it will convert them to Boolean array, split the array to extract the 10 bits for determining case number and remaining 54 for control values. I know that that 54 bits may not be sufficient if number of controls in one particular case is more.

By the way all the cases will now have a crazy 64 representation. Suppose I want to generate a TTL pulse of 1 µs given that case 1 is switch ON the TTL signal, case 2 is wait, case 3 is switch off. Then the binary code is :

For Switch ON : 0000000001000000000000000000000000000000000000000000000000000000

For 1 µs wait : 0000000010000000000000000000000000000000000000000000000000000001

For Switch OFF : 0000000011000000000000000000000000000000000000000000000000000000

For this operation, decimal numbers given to the FPGA via DMA FIFO are:

For Switch ON : 18014398509481984

For 1 µs wait : 36028797018963969

For Switch OFF : 54043195528445952

The advantage now is using the same wait case I can generate any number of TTL pulse duration one after another. Say first a 1 µs TTL pulse, Then wait for 1 µs and generate another 2 µs TTL pulse. The code given to the FPGA is :

For Switch ON : 18014398509481984

For 1 µs wait : 36028797018963969

For Switch OFF : 54043195528445952

For 1 µs wait : 36028797018963969

For Switch ON : 18014398509481984

For 2 µs wait : 36028797018963970

For Switch OFF : 54043195528445952

I have tested this method with a case having four control values in non-integer format also (e.g. 8.8, 4.76 etc.). Using partitioning of the 64 bits of U64 integer, I can rebuild the integer and non-integer part of a real number in FPGA once I recieve the U64 integer. I would like your reviews on this method.

And finally I have some more questions :

Q.1. How many number of different DMA FIFOs we can use? Is there a specific answer for my hardware configuration given at the begining of this conversation list?

Q.2. When I use a DAQ card to gnerate say a continuous train of TTL signals, does it use the computer clock or its own clock like an FPGA card?