Coregen out of memory when using VI defined Block Memory

[BrianMZA]

I am currently encountering an issue when trying to compile a VI for my Flex RIO card (PXIe-7965R).  I have a sub-vi that contains a small instance of VI-defined memory (U16 X 256 elements) and a DSP48 block.  This VI is instantiated 128 times in the top level VI.  When I configure the VI-defined memory to target the Block RAM in the FPGA, the compile process hangs when generating cores (out of memory after ~ 45 mins).  Does LabVIEW treat each of the instances of the block memory as unique when running coregen?  I do not encounter this issue when I configure the VI-defined memory to use LUTs.  Any thoughts would be appreciated.

Thank you,

Brian

[Blayne_K · Accepted solution]

Hi Brian,

I believe this compilation failure might be less related to the coregen memory implementation, rather the way memory is implemented in LUTs and Block memory on a FPGA. LUTs are constructed through flip flops and are most suitable for storing information 100-300 bytes in size, whereas block memory is chunked into embedded RAM of a fixed size of 2KB. One only has a certain number of Block RAM structures in a given FPGA and it seems in your case you are using up more than your allotted Block RAM resources. For example, in the 7831R if one was attempting to implement a FIFO in Block memory the maximum possible storage size would be 81,920 bytes due to the limitation in resources.

The flip flop implementation of the LUTs will allow the compiler more flexibility in utilizing resources in compilation because the size of the LUT is not fixed in the way a Block RAM structure is. This is likely the reason why that LUT implementation is successfully compiling while the Block RAM in this case is not. 

Regards,

Blayne K

[BrianMZA]

Blayne -

Thank you for the detailed reply.  I suspected that the limited Block RAM resources could have been the problem, but it manifested itself in a strange way by running out of memory during the coregen step.  I am up and running successfully with a LUT RAM implementation, but it sure does eat a lot of resources on the FPGA.  On the positive side, the memory read access doesn't have to be pipelined with a register like it does with the Block RAM.

Thanks again,

Brian