LabVIEW
DAM FIFO Error 50400 - PXI 7813R
Hi,
I have been trying to use a DMA FIFO to transport data between the target (FPGA) and host (windows). The setup of the FIFO is shown below.
The FIFO write at the target is as follows.
The FIFO read at the host is as follows.
I have been recieving the followwing error:
Error - 50400 occurred at nirio_DMARead.vi:1
Possible reason(s)
The transfer did not complete within the timeout period or
within the specified number of retries.
I understand that the FIFO is not acquiring enough elements, but I do not understand how to fix the problem.
If anybody has a suggestion as to how I might fix this problem I would be most appreciative 
Thanks for taking the time to read the post,
Michael.
Message Edited by Michael_Limerick on 05-07-2008 02:28 AM
Message Edited by Michael_Limerick on 05-07-2008 02:33 AM
The FIFO write at the target is as follows.
The FIFO read at the host is as follows.
I have been recieving the followwing error:
Error - 50400 occurred at nirio_DMARead.vi:1
Possible reason(s)
The transfer did not complete within the timeout period or
within the specified number of retries.
I understand that the FIFO is not acquiring enough elements, but I do not understand how to fix the problem.
If anybody has a suggestion as to how I might fix this problem I would be most appreciative
Thanks for taking the time to read the post,
Michael.
Message Edited by Michael_Limerick on 05-07-2008 02:28 AMMessage Edited by Michael_Limerick on 05-07-2008 02:33 AM
Apologies for the DOUBLE post, the original post may have been a little difficult to read, here it is a bit easier to read.
Hi,
I have been trying to use a DMA FIFO to transport data between the target (FPGA) and host (windows). The setup of the FIFO is shown below.
The FIFO write at the target is as follows.
The FIFO read at the host is as follows.
I have been recieving the followwing error:
Error - 50400 occurred at nirio_DMARead.vi:1
Possible reason(s)
The transfer did not complete within the timeout period or
within the specified number of retries.
I understand that the FIFO is not acquiring enough elements, but I do not understand how to fix the problem.
If anybody has a suggestion as to how I might fix this problem I would be most appreciative
Thanks for taking the time to read the post,
Michael.
Hi,
I have been trying to use a DMA FIFO to transport data between the target (FPGA) and host (windows). The setup of the FIFO is shown below.
The FIFO write at the target is as follows.
The FIFO read at the host is as follows.
I have been recieving the followwing error:
Error - 50400 occurred at nirio_DMARead.vi:1
Possible reason(s)
The transfer did not complete within the timeout period or
within the specified number of retries.
I understand that the FIFO is not acquiring enough elements, but I do not understand how to fix the problem.
If anybody has a suggestion as to how I might fix this problem I would be most appreciative
Thanks for taking the time to read the post,
Michael.
