Filipe,
Your assumptions that the PCI-6025E board cannot perform the task that Lyn requires are incorrect.
You are correct in stating that the PCI-6025E does not support buffered I/O operations, but there are no indications in the question posed by Lyn to suggest that this is the requirement for the application.
Example: If I wanted to acquire 1000 state changes made by some external hardware at a rate of 1 state change per second, would I need to consider using a buffered operation for this task?
I would suggest that the answer to this is no.
The rate at which the data is being generated compared to the rate at which the data can be acquired is one of the fundamental issues that determines whether a buffered acquisition is required or not. This is true for AI/AO/DI/DO and CTR operations.
So referring to my previous example, if my software application had difficulty keeping up with 1 reading per second, I would need to consider using a buffered read operation, otherwise a simple handshake operation with the external device could be considered.
I would suggest looking through Application Note 131 which breaks down the various types of digital I/O applications that one might encounter (also covered on the NI Data Acquisition training course, if my memory serves me correctly?)
The PCI-6025E uses an 8255 PPI to provide the additional 24 DIO lines. The 8255 can be configured to operate in handshake/bidirectional mode (modes 1 and 2) and as such can be used to handshake data either from or to an external source. The PCI-6023/24/25E User Manual documents the assignments for the lines on Port C when configured for mode 1 or 2.
With reference to AN131 - this type of operation available on the PCI-6025E is referred to as Block I/O.
The rate at which this block I/O operation can take place will be primarily dependent on the speed at which blocks of data can be read by the software controlling the PCI-6025E (LabVIEW in this instance).
Now if the statement was I need to read back 1000 blocks of data across 2 ports at a bit rate of 0.5Mbits/second, then I would agree that a buffered read operation should be considered and that this would be beyond the task of the PCI-6025E.
It should be appreciated that not everybody provides every single bit of information in questions raised on Developer Zone. Those with application knowledge will recognise this fact and request for more information to be supplied, rather than simply making assumptions that the board that they have purchased is incorrect.
