Latency / Bandwidth are often tradeoffs.
What are you trying to accomplish? While a Front Panel control typically has a lower latency than a DMA, once you compare 20 Front Panel controls to a single DMA with 20 elements, it flips quickly.
Handshake logic, AFAIK does not exist between RT and FPGA per se, but can be made up of items of the other types. Handshakes are to my knowledge a FPGA-intern signalling pathway.
I have never used an Interrupt. Latency is similar to that of a Front Panel control, and have never had need for the synchronising aspect of the Interrupt.
I have once posted a test of DMA bandwidth / latency measurements for a given system. Latency and Bandwidth are dependent on several factors including:
- FPGA target
- Chassis (PXI_E Generation and speed)
- Presence of a PCI-PXI-E Bridge chip
- Controller
All of these can have a negative influence on the theoretical maximum performance. As such, I would recommend testing systems as a whole even if having some "rules of thumb" can still prove useful.
