Dear comunity, I am reading 8 AI with the CRIO at high frequency corresponding to 8 sinusoidal waves from resolvers. Also, I am doing some operations in the FPGA and passing to the RT host 2 FIFOs. One is called resolvers with those 8 channels and the other is called speed and accel. which has 12 channels with 4 angular positions, 4 speeds and 4 accelerations in that order. When I read both FIFOs with the host I wait for the FIFO to have enough elements. I also set the timeout of the FPGA to -1 to avoid problems altought I do not know very well what to select. The problem is that when I read with the Host, the channels do not keep the original order which I used for assembling them in the FPGA and also it is possible to appreciate swithings between channels every few seconds so the information is not consistent and robust. It is not possible to use the information if the channels do not stop changing their relative position. I would appreciate any ideas in solving this and in incrementing the RT frequency because it is going at maximun of 60 Hz, where I was expecting much more. Thank you very much. Regards Enrique

@EnrikDS wrote: Hi, attached are two images to explain which parameters I am using to configure the FIFO. We can focus on the speed FIFO: -Depth confgured to: 120000 -Number of element in a read instruction: 1200 The FIFO can also be configured in the project explorer, in fact I am not sure if the depth parameter configured in the Block Diagram means the same than the parameter "Requested number of elements" which appears when you double click in the FIFO at the Project Explorer, that value is 4095. Other values are: -Target to Host -Data type: FXP (64 bits, 32 bits) I hope this helps. Thank you very much for your support. Enrique When you configure the FIFO from the project expolorer you are defining how much FPGA space to use for the FIFO for buffering before the data is duplicated into the RAM FIFO defined by the property node. Have you tried setting the time out of the FPGA FIFO write to 0, this would be a lossy FIFO. You can use the FIFO.GetNumberofElementstoWrite to query how much space is in the FIFO and only write when you have 8 and 12 elements free.

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DMA FIFO switching beteen channels after FPGA sends

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Thank you for responding crossrulz.

Sir i have constrains from my organisation, regarding sharing the code. So will it do, if send the code in private msg in jpg form

to you on your account

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DMA FIFO switching beteen channels after FPGA sends

Re: DMA FIFO switching beteen channels after FPGA sends