Data Logging Issue with FPGA using CRIO. TDMS results attached.

[PG416]

Hi,

I am having an issue with the attached LABVIEW project.

I am using Ni cRIO-9035. I would like to take a sample of 200 data points at a sample rate of Y (where, Y is less than the 40 MHz sampling rate of the cRIO). The samples would be taken 1 second apart and I would like to be able to specify via the GUI how many samples to take.

In general, the code seems to be working. The main issue, I am having is with the recorded data samples from the 6 analog channels. The values should be sinusoidal 60 Hz waveforms; however, looking at the results in the .tdms file it seems that maybe there is an underlying sinusoidal waveform; however, the data points are quite randomly distributed.

Perhaps I am logging the data points incorrectly? Any suggestions would be helpful.

Thanks,

Phil

[JensG69]

Which analog-in module are you using. Also the FPGA is able to run at 40 Mhz (or even faster), the analog-in module usually is not.

In addition it is recommended to use the "loop timer" in the first case of a flat sequence inside the FPGA code.

Regards, Jens

[PG416]

Hi Jens. Thank you for the fast response.

I am using 2 x NI 9215. I would like to read the 200 measurements at a sampling rate above 8 kHz.

[PG416]

Hi. I tried moving the loop count frame before the FIFO write frame as suggested. Unfortunately, still not working. Does anyone have any other suggestions?

I should note that the FIFO on the FPGA2.vi file is timing out.

Cheers,

Phil

[PG416]

Bump.

[SaileshK]

Hi Phil,

Do you get any errors during runtime? Has this project worked properly in the past?

[Amrit_11]

Hi Sailesh,

Project seems to run just fine. However, note the RT4 the "Timed Out?" indicator gets flagged at run-time.

I will send you a PM Sailesh.

Cheers,

Phil