Disappointed annoyed and angry:: merge labview fpga with vhdl through ip block

[mangood]

final i get the problem 
the sfixed comparator is not working in IP block when implementation 
for example this code 

es <= "0001" when (suma =4) else
"0010" when (suma =-4) else
"1111";

 wil work in simautlion but in hardware will fail
so the comparator must be converted to STD_LOGIC vectore to solve that
this Serious violation occurred that is not reported by NI

[david1147]

Generally speaking, IP Integration Node is only an integration tool that brings in 3rd-party IP, and then passes it on to Xilinx tool chain (both simulation and compilation). It would be good if you develop your IP in tool vendor's environment and verify it there before you integrating it into LabVIEW. IP Integration Node itself is not so strong in IP development phase.

[Dragis]

I will second that any IP brought in using the IP Integration Node (IPIN) should be thoroughly tested with the vendor tools if possible before importing into LabVIEW. This IP is effectively a black box to LabVIEW so any problems will be very hard to debug after the IP is imported. It is possible to synthesize individual blocks for hardware and run simulations throughout the flow to ensure they are functionally correct and meet all the protocols required by LabVIEW FPGA.