I managed to find a solution that would work for my application, but I can see how this might not work for others in a variety of applications...
I need to make a few sets of measurements, in no particular order - all DIO at the 3.3V logic family, then with half at 1.2 and the other at 3.3, then swap the halves (so the first half uses 3.3, the other 1.2). These measurements are done the exact same way regardless of logic family, so I reused the same VI for these steps...
-To run the first set, I left the I/O configuration alone (3.3V logic family) and compiled the bitfile from the VI.
After compiling, I set the changed the logic family of "the first half" of my DIO ports to 1.2V (right click on the FPGA target in the Project Explorer window, click Change I/O Configuration...).
-I saved all project items, then created a new build spec, which created a different bitfile (I'm not convinced the new build spec required to create a new build spec, but I think the critical piece is that a different bitfile gets created).
-After that bitfile was generated, I changed the logic families again and generated my third bitfile.
-In my host (Windows) VI, I launch the three FPGA VI instances (using Open FPGA VI Reference.vi) by specifying the VI's by bitfiles. I point it to the three bitfiles that use the different logic family settings in these calls.
