ERROR: [Synth 8-5809] in FPGA Complation

[jiangliang]

Hello:

When i'm using FlexRIO with Cameralink 1483, I got a xilinx compile error says Error 8-5809.

I can successly compile some simpler VI in the same project, and the failed one is only using more resource, more logic, no odd things like CLIP or XIP has been added. 

And the log says there are problem in interface.vhd, I checked this file and it a file comes with LabVIEW FPGA, encrypted, can't say there is anything wrong with that. 

I compared the Interface.vhd of a working VI, the difference is working VI get me a Interface.vhd of bytes = 28752, and the one with error have a Interface.vhd bytes = 38240? Is this the reason my VI fail to compile? I did add 5 FIFOs in VI-scope to add some function, Also I added 4 FIFO to host (which should be fine since FlexRIO Controller should have 16 or maybe more DMA channel).

Can anyone give me some advice? Thanks!

Here is the compile result:

LabVIEW FPGA: The compilation failed due to a Xilinx error.

Details:
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/K0WSe4L_wgI55K2/Interface.vhd:445]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/K0WSe4L_wgI55K2/Interface.vhd:446]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/K0WSe4L_wgI55K2/Interface.vhd:447]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/K0WSe4L_wgI55K2/Interface.vhd:448]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 385.238 ; gain = 154.605
---------------------------------------------------------------------------------
RTL Elaboration failed
2 Infos, 0 Warnings, 0 Critical Warnings and 5 Errors encountered.
synth_design failed
::RTL Elaboration failed
while executing
"source -notrace {C:/NIFPGA/jobs/K0WSe4L_wgI55K2/.Xil/Vivado-22556-Laptop-G7/realtime\SmallBlockTop.tcl}"
invoked from within
"synth_design -keep_equivalent_registers -top "SmallBlockTop" -part "xc7k410tffg900-2" -flatten_hierarchy "full""
(file "C:/NIFPGA/jobs/K0WSe4L_wgI55K2/synthesize.tcl" line 31)
invoked from within
"source "C:/NIFPGA/jobs/K0WSe4L_wgI55K2/synthesize.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Fri Dec 13 15:28:43 2019...

Compilation Time
---------------------------
Date submitted: 12/13/2019 3:27 PM
Date results were retrieved: 12/13/2019 3:28 PM
Time waiting in queue: 00:08
Time compiling: 01:05
- Generate Xilinx IP: 00:00
- Synthesize - Vivado: 00:56

-------------------------------------------------------------------------------------------------------

and there is the Xilinx log:

WARNING: Default location for XILINX_VIVADO_HLS not found: 

WARNING: [Common 17-306] Update version (2017.2.1_AR70173) does not match product version (2017.2.1).

WARNING: [Common 17-306] Update version (2017.2.1_AR70069) does not match product version (2017.2.1).

WARNING: [Common 17-306] Update version (2017.2.1_AR69663) does not match product version (2017.2.1).

****** Vivado v2017.2.1_AR71289_AR70173_AR70069_AR69663_AR69485 (64-bit)

  **** SW Build 1957588 on Wed Aug  9 16:32:24 MDT 2017

  **** IP Build 1948039 on Wed Aug  9 18:19:28 MDT 2017

    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

INFO: [Common 17-1460] Use of init.tcl in C:/NIFPGA/programs/Vivado2017_2/scripts/init.tcl is deprecated. Please use Vivado_init.tcl 

Sourcing tcl script 'C:/NIFPGA/programs/Vivado2017_2/scripts/init.tcl'

# package require struct::list

# package require struct::set

# set_param synth.elaboration.rodinMoreOptions "rt::set_parameter max_loop_limit 1000000;"

# ::struct::set add vhd_files [glob *.\[vV\]\[hH\]\[dD\]]

# ::struct::set subtract vhd_files {"BuiltinFIFOCoreFPGAwFIFOn0.vhd" "BuiltinFIFOCoreFPGAwFIFOn1.vhd" "BuiltinFIFOCoreFPGAwFIFOn11.vhd" "BuiltinFIFOCoreFPGAwFIFOn5.vhd" "BuiltinFIFOCoreFPGAwFIFOn6.vhd" "BuiltinFIFOCoreFPGAwFIFOn9.vhd"}

# read_vhdl $vhd_files

# if {[llength [glob -nocomplain *.\[xX\]\[dD\]\[cC\]]] > 0} {

#     set CoreXDCFilesFH [open CoreXDCList.txt r]

#     set xdc_files_xci [split [read $CoreXDCFilesFH] "\n"]

#     close $CoreXDCFilesFH

#     set xdc_files_all [glob *.\[xX\]\[dD\]\[cC\]]

#     set xdc_files_source [::struct::set difference $xdc_files_all $xdc_files_xci]

#     set xdc_files [read_xdc $xdc_files_source]

#     foreach xdc_file $xdc_files_xci {

#         if {[file exists $xdc_file]} {

#             lappend xdc_files [read_xdc -ref [file rootname $xdc_file] $xdc_file]

#         }

#     }

#     set_property PROCESSING_ORDER {LATE} [get_files $xdc_files]

# }

# read_edif [glob *.\[eE\]\[dD\]\[fFnN\]]

# read_edif [glob *.\[eE\]\[dD\]\[iI\]\[fF\]]

# read_checkpoint "BuiltinFIFOCoreFPGAwFIFOn0.dcp"

Command: read_checkpoint BuiltinFIFOCoreFPGAwFIFOn0.dcp

WARNING: [Vivado 12-4167] The checkpoint part 'xc7k410tffg900-2' does not match the current project part 'xc7vx485tffg1157-1'.

# read_checkpoint "BuiltinFIFOCoreFPGAwFIFOn1.dcp"

Command: read_checkpoint BuiltinFIFOCoreFPGAwFIFOn1.dcp

WARNING: [Vivado 12-4167] The checkpoint part 'xc7k410tffg900-2' does not match the current project part 'xc7vx485tffg1157-1'.

# read_checkpoint "BuiltinFIFOCoreFPGAwFIFOn11.dcp"

Command: read_checkpoint BuiltinFIFOCoreFPGAwFIFOn11.dcp

WARNING: [Vivado 12-4167] The checkpoint part 'xc7k410tffg900-2' does not match the current project part 'xc7vx485tffg1157-1'.

# read_checkpoint "BuiltinFIFOCoreFPGAwFIFOn5.dcp"

Command: read_checkpoint BuiltinFIFOCoreFPGAwFIFOn5.dcp

WARNING: [Vivado 12-4167] The checkpoint part 'xc7k410tffg900-2' does not match the current project part 'xc7vx485tffg1157-1'.

# read_checkpoint "BuiltinFIFOCoreFPGAwFIFOn6.dcp"

Command: read_checkpoint BuiltinFIFOCoreFPGAwFIFOn6.dcp

WARNING: [Vivado 12-4167] The checkpoint part 'xc7k410tffg900-2' does not match the current project part 'xc7vx485tffg1157-1'.

# read_checkpoint "BuiltinFIFOCoreFPGAwFIFOn9.dcp"

Command: read_checkpoint BuiltinFIFOCoreFPGAwFIFOn9.dcp

WARNING: [Vivado 12-4167] The checkpoint part 'xc7k410tffg900-2' does not match the current project part 'xc7vx485tffg1157-1'.

# set_msg_config -id "Synth 8-3431" -suppress

# synth_design -keep_equivalent_registers -top "SmallBlockTop" -part "xc7k410tffg900-2" -flatten_hierarchy "full"

Command: synth_design -keep_equivalent_registers -top SmallBlockTop -part xc7k410tffg900-2 -flatten_hierarchy full

Starting synth_design

Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t-ffg900'

INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t-ffg900'

INFO: [Common 17-1223] The version limit for your license is '2017.12' and will expire in -712 days. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.

INFO: Launching helper process for spawning children vivado processes

INFO: Helper process launched with PID 24024 

---------------------------------------------------------------------------------

Starting RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 314.422 ; gain = 83.789

---------------------------------------------------------------------------------

ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/K0WSe4L_wgI55K2/Interface.vhd:445]

ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/K0WSe4L_wgI55K2/Interface.vhd:446]

ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/K0WSe4L_wgI55K2/Interface.vhd:447]

ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/K0WSe4L_wgI55K2/Interface.vhd:448]

---------------------------------------------------------------------------------

Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 385.238 ; gain = 154.605

---------------------------------------------------------------------------------

RTL Elaboration failed

2 Infos, 0 Warnings, 0 Critical Warnings and 5 Errors encountered.

synth_design failed

::RTL Elaboration failed

    while executing

"source -notrace {C:/NIFPGA/jobs/K0WSe4L_wgI55K2/.Xil/Vivado-22556-Laptop-G7/realtime\SmallBlockTop.tcl}"

    invoked from within

"synth_design -keep_equivalent_registers -top "SmallBlockTop" -part "xc7k410tffg900-2" -flatten_hierarchy "full""

    (file "C:/NIFPGA/jobs/K0WSe4L_wgI55K2/synthesize.tcl" line 31)

    invoked from within

"source "C:/NIFPGA/jobs/K0WSe4L_wgI55K2/synthesize.tcl""

# exit

INFO: [Common 17-206] Exiting Vivado at Fri Dec 13 15:28:43 2019...

[az_ltr]

I got this error too.  For me it seems as if I had the same resources in different SCTL.  When I removed the SCTL I synthesized OK.  I really do not need SCTLs for now so I just removed them.  The meaning of the error is unknown but at least for me it was related to having resources in SCTL.

[BEZENCHUK]

did you find a solution? i have the same problem: "...does not match the current project part 'xc7vx485tffg1157-1". 

I have 2 cycles SCTL . The first cycle with the core with the frequency from the generator. The second cycle with the DAC with the daughter frequency. In this form it does not compile. If I combine them into one cycle, it also does not compile.

[Intaris]

If you can post some code / images of your code, there might be a better chance of understanding where the issue might be coming from....

In cases like this, it helps to export the project to Vivado, open it there (With the Vivado installed in your C:\NIFPGA folder) and perform synthesis with the synthesis option "Flatten" set to "none". Then do the implementation (if is succeeds) and from there you can locate where the errors come from. Vivado can show a bit more information on what has gone wrong. It doesn't always help, but it can be a huge help to get beyond the "encrypted envelope error" which can have a bazillion different causes.

[BEZENCHUK]

The project is developed on the basis of the Ettus USRP x410 device (RFSoc, zynq ultrascale plus). The project implements a DVB-S2 signal modulator. Here I am talking about its FPGA part and not touching on the HOST part.

The project consists of 2 clock domains.
Inside the first domain at a frequency of 125 MHz is the IP core of the DVB-S2 modulator and a pseudo-random sequence generator of 8 bits. Inside the second, child clock domain at the same frequency of 125 MHz is a fractional interpolator and DAC. Data transfer between domains is performed via FIFO target-scoped.

The DVB-S2 algorithm is a ready-made IP core in the vhdl language. To embed the IP core in the IP Integration Node block, a .dsp file is used after synthesizing the IP core project in vivado. Previously, the project was successfully compiled and worked.

At a certain point, the project stopped compiling, although there were no significant changes. Previously the project compiled successfully. At the same time, the amount of FPGA resources used changed dramatically. At the same time, the compilation strategy began to be automatically selected for the user with aggressive options instead of the default strategy.
One of the warnings is the following at the beginning of the compilation: "The checkpoint part, xczu28dr-ffvg1517-1-e, does not match current project part, xc7vx485tffg1157-1".

xczu28dr-ffvg1517-1-e is RFSoc, zynq ultrascale plus. xc7vx485tffg1157-1 is another board, which has never been in my project. However, it was later discovered that this warning was also in older versions of the project, when the program compiled successfully. Now these previously working versions, as well as later versions, compile with errors (placement errors).

Reinstalling Labview and creating a new project did not help, the result is the same.

In Vivado, the project files are exported encrypted, so I do not understand what is in them.
The project synthesis in Vivado is successful, the implementation without disabling the flatten option was with an error, with the flatten option disabled the error is gone (thank you). When synthesizing an exported project in Vivado, the number of used resources is much less (screenshots),
than during implementation, which is suspicious. For example, the number of DSP blocks = 184 during synthesis in Vivado, and 1178 during implementation.
This coincides with the resources of an unsuccessful compilation in LabView (final utilization)

Also a question, can I somehow use a bitstream file from Vivado for the Host program in LabView? As far as I understand, I can only use .lvbitx files.

[Intaris]

I'm glad the "flatten option = off" helped, but that's actually not what I was suggesting / expecting. I meant is purely as a means of perhaps getting a more detailed error from Vivado.....

We have also had different encrypted envelope errors over the years. Some come down to invalid VHDL constructs which LabVIEW does not catch before passing off to Vivado. It then generates invalid code for itself (within the encrypted portion) and then throws the incredibly useful error "encrypted envelope error".  BTW, I presume you already know this but any VHDL files you label with "UserRTL_" as prefix will NOT be encrypted in a Vivado compilation.... We do this for all of our VHDL code and it enables us to at least get proper error codes for OUR VHDL code, even if from time to time encrypted envelope errors can still arise. Also, the fact that the implementation lists significantly more resources than the synthesis is also true for our code, but it has been this way for years and we don't typically have issues with compilation. I think it requires more analysis of some VHDL portions to accurately ascertain the usage and this only happens later in the compilation chain.

Your compilation seems to have unplaceable I/O resources.... This was the first error I found in your log.

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
ERROR: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0).
The following are banks with available pins:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: Out RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 1 sites.
Term: QSFP1_3_TX_P

ERROR: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0).
The following are banks with available pins:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: Out RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 1 sites.
Term: QSFP1_3_TX_P

ERROR: [Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

Don't know what to recommend at this point, I don't know your design at all. To my relatively untrained eye, I'd start looking if you're trying to utilise pins within a single bank with different incompatible standards (LVCMOS12 and LVCMOS18).

Also, if your previously compiled source no longer compiles I would suggest something may have changed that you have overlooked. Sometimes a minor change can lead to something being removed by Xilinx due to inactivity or something which was previously removed no longer being removed by simply adding a connection to the code.

One conspiracy-level thing I've noticed with cloud compiles is that compiling from a new directory sometimes yields different results. Or creating a new build spec and then compiling from there. I think this is connected to the fact that the compile servers also have a "compile" cache and changing name of the compilation is akin to clearing this cache for the new compilation. This shouldn't make a difference, but it seems to have -some- level of effect. Not something to do on the regular but when stuck unable to compile... maybe it's worth a shot.

[BEZENCHUK]

vhdl code is essentially a black box (signal generation) that I embed into the USRP x410 device.

I don't know if it matters, but my code is compiled on my computer, not in the cloud.

The vivado I/O resources look like this (screenshot). how can I fix this in labview?

[Intaris]

This is beyond my expertise, but what's hidden behind the section where "multiple" is written in red?

[BEZENCHUK]

Here is a snapshot with an expanded list of the row "multiple"

Also, when trying to debug the program in simulation mode through controls, indicators and invoker method, the following error message appears. This error appeared in the simulation at the same time as the program stopped compiling. The picture shows the part of the Host program that appears at the exit of the "ni USRP Opens a Tx session with a custom bit file" block"

[Intaris]

Sorry, I've used up all of my knowledge of this topic.... Anything I'd say from now on would be pure speculation.

Hopefully someone else can pop by and help.