Easier more elegant way to instantiating two CLIPs?

[T-REX$]

Unfortunately, I can't think of a good way to instantiate DMA FIFOs from the block diagram. They are strictly project items as well.

One design/framework that has been done to get around this is the register bus library

It's not really designed for streaming data, but basically provides a mechanism to route data through a single DMA channel to multiple parts of your design. It's a bit complex, but once you get the basics of the architecture, I think it's easy enough to use and implement. It may not really fit the requirements for your application if you're using the DMA channels for streaming large amounts of data.

[RichC41]

I'm going to mark the IPIL vs. CLIP comment as the solution even though I'm still investigating its implemetation.  I think that's going to fix me up though, I bet a large part of my issues are the difference between the way labVIEW handles the data dependencies