Erratic FIFO behavior

[Intaris · Accepted solution]

You need to latch the "FIFO Full" indicator to see if at any time your FIFO was full.

If you don't implement some kind of iterative "hold" for situations where the FIFO is full, then a single "Full" status will cause your data to be incorrectly interleaved in your FIFO.

We use a system where we do not use a FOR loop but we iterate in a while loop and step through the elements to be sent. If any single element returns a "Full" signal, we stay on that index until the FIFO write is successful. This way the order of data int he FIFO remains intact.

[ScottR22]

I'll put on monitor on it to alert me if this occurs, thank you for the suggestion. However, if that is what in fact is happening, which I doubt as I have a FIFO buffer set to 10M, does your iterative while loop ever show the FIFO full?

[ScottR22]

I've updated my FPGA code I think in line with your suggestions. One question I have for you is what if the re-iteration causes the time to process the array completely exceeds the 1000Hz (1ms) rate I have my outer loop set to execute at? Wouldn't that throw off the timing of the data. The biggest reason I moved the data collection to the FPGA in this project was because I needed to be able to count on the data being HW timed and accurate for slew rate calculations, etc...

Appreciate your help and suggestions.

[Intaris]

Your implementation for preventing the problem of losing FIFO elements looks good.

Your code on the RT needs to read data fast enough to prevent backing up in the FIFO. Ideally, Timeout should never happen. But in reality, it might.

If you start losing data, you lose an iteration. But this only happens if you cannot process the data fully anyway. It's better to fail gracefully (Losing data) rather than failing catastrophically (reading wrong data- and potentially not realising).

You still need to process fast enough to prevent backing up your FIFO. The method I mentioned just allows you to handle the failures more gracefully.

[ScottR22]

Well, my element count on the RT side shows less than 300k elements of SGL (4 bytes) data types for tests lasting 30 seconds or less, my buffer is set to 10M, I can't imagine that ever getting full at that size, but I will see how these new changes work.

Thanks for all your assistance.

[ScottR22]

The changes I've implemented appear to have solved the issue, thank you very much for your assistance.