FFTs on multiple channels in FPGA

[Jed_Davidow]

I have a customer with a 9076 (Spartan-6 LX45) that would like to perform FFTs on multiple channels of a 9205 module.

I have never run FFTs on multiple channels, and never run out of space on the FPGA before, but I strongly suspect that this might change that.  Before I start coding this and playing around, does anyone have experience with this scenario- can you suggest an optimal architecture/let me know how many channels I can expect to process?

[T-REX$ · Accepted solution]

Hey Jed,

As someone who has done a very similar app, but with DC/RMS measurements, I can say with confidence that yes, this will change that... How many channels does your customer want to do, and what kind of throughput? I was able to get up to 64 going, but it took most all of the fabric, and I had to write my own multiplexed DC/RMS calculation VI. So less throughput of course (I think we had each channel update at 1Hz with 1000 samples per channel). So, by writing a VI that multiplexes through all the channel data, you could theoretically get a lot of channels on there, but you sacrifice throughput.

Basically I modified the existing Express VI to store it's state in BRAM between each call, and iterated through it for the number of Channels*Samples I was doing. Not terribly difficult, but time consuming trying to find a good balance for the given application.

[Jed_Davidow]

I'm trying to interpret what you are saying- essentially that you modified the FFT express VI to chug through multiple data streams.  To do this, each channel's individual "FFT state" needs to be cached for each iteration.  The "hope" is that the FFT engine is running at 40MHz but the acquisition is running at 1000Hz.  Using a 1Hz final output interval, you have 40M cycles to compute the FFTs for all the channels.  In this way, you can clock out the interlaced data from a FIFO.

This seems like a pretty robust solution (assuming the desired number of channels can be processed in time).  Do you have an example that I could look at?  I haven't worked with BRAM before.

I suppose this could easily be modified to run multiple "pipelines" in parallel, if the FPGA has the resources?

[Jed_Davidow]

I think I found an (possibly the) example.  It doesn't interlace the calculation, but serializes them, storing the acquired data in VI-scoped FIFOs until it's ready to be read for that channel.

This looks useable- I think I can make it work. 

Thank you for the info!

[T-REX$]

Awesome, I hope it works for you. Like I said, my example (attached below) was using the DC/RMS calculation VI, but the serialization principle is the same. I remember I did quite a bit of commenting on the top-level, but when you dig down into the actual algorithm, there isn't much info. Basically I just took what was already there, and made it store its state between iterations (since each calculation for each channel is dependant on the last value for that channel). Good luck!