FIFO DMA FPGA

[FrankyCam]

I'm working to FPGA on C-rio in order to acquire high speed data from piezo load cells. I'm using FIFO-DMA variable to exchange data between FPGA and C-rio. In FIFO settings the fields 'Requested number of elements' appears. What is its meaning? What are 'elements'?

Thank you

Francesco

[Larry.C]

Hello FrankyCam,

When you create a FIFO DMA you need to allocate how much memory you will use in that FIFO for your data. The requested number of element field dictates the maximum number of data points you can store in that FIFO before it overflows.

It is important to try and allocate as little memory to the FIFO as possible (since there is limited memory on the FPGA), however you should not let it overflow otherwise you will lose the data being sent to the FIFO.

I hope this information helps you understand. If you have any more queries please do not hesitate to post.

Regards,

Laurence C.

Applications Engineer

National Instruments UK

[FrankyCam]

I'm using Ni9239 Analogue input 4 channel 24 bit, sampling 50KS/s. Bit rate should be 24bit/S*50KS/s=1200Kbit/s=150Kbyte/s. How i can chose number of element in FIFO-DMA?

Thanks

F.

[Larry.C]

Hi FrankyCam,

I believe I understand the situation to be as follows:

You are recording data into a FIFO of which the data type is 24 bits in size. You are then trying to place the data onto the FIFO at a rate of 50 samples per sec.

The requested number of elements is chosen by looking at how quickly the data will be read from the FIFO on the host VI. If you are placing 50 samples onto the FIFO every second but are also reading 50 samples per second you will need a minimum of 50 elements. However due to synchronisation there may be more data passed onto the FIFO before it has read all 50, hence you should increase the number of elements to allow for this type of shift. If your program requires very little memory from the FPGA you might as well put a high number of elements in to account for any fluctuations in the FIFO queue.

I advise to play around and try different numbers since if an overflow (or underflow) error occurs you can set up your code to prompt you, after which you could increase the number of elements to match. The Timeout node on the FIFO specifies the time, in number of clock ticks, that the method waits for available space in the FIFO if the FIFO is full. A value of –1 prevents the function from timing out. If you are checking for overflow you could put a timeout of 0 meaning that when the FIFO is full it will immediately pass out an error which you could use.

I hope this covers what you are asking, if you need more advice please do not hesitate to post.

Regards,

Laurence C.

Applications Engineer

National Instruments UK

P.S. A good way of matching up the number of elements to read to the number of elements to write is by wiring the "elements remaining" node on an invoke method to the "number of elements" node so that it will read the number of elements off the FIFO that the FIFO has remaining (meaning you will read all data).

[FrankyCam]

NI9239 samples 50kS/s=50000S/s and not 50 sample per second...

F.

[Larry.C]

Hi FrankyCam,

I apologise for my silly mistake. If you apply the same idea though (as above) but change it for 50k samples it should work.

If you are having problems I would me more than happy to help.

Regards,

[FrankyCam]

I refer to the value in red circle in figure...so i should change this value into 50000 ?

[Larry.C]

Hi Franky,

Yes if you change the value to 50k you should have a FIFO big enough to store your information. Note that when you do assign 50k that the actual number of elements will be 65535 (can be seen 2 boxes down in grey) as the memory is reserved in blocks of square numbers (256^2).

I hope this works!

Regards,

[FrankyCam]

Buto in a Labview guide http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgadialog/fifo_general_page/  I found this:

Requested Number of Elements—Specifies the desired number of elements the FIFO can hold. The maximum number of elements the FIFO can hold depends on the Implementation you select and the amount of space available on the FPGA for the Implementation. If the FIFO uses built-in control logic, the maximum number of elements also depends on the data type. The width of the built-in FIFO must be less than or equal to 1024.

Sorry for my repeating question..

F.

[Dragis]

Hi FrankyCam,

Most of the boards are capable of sustained DMA throughput from FPGA to Host of > 100 MB/s, so you should have no trouble transferring your 24 bit data to host at 50 kS/s. The DMA channels use the Block Ram built into the FPGA which comes in chunks of ~ 16 kb for older familes and ~ 32 kb for newer familes but at data widths on power of 2 boundaries. So in your case 16k / 32 ~ 512 elements within a single Block Ram which should be more than enough room. 

Also, remember that there is a large data buffer on the host side (by default 10,000 elements). The DMA engine starts transferring the data from the FPGA to the Host as soon as it is available regardless of whether your reading the data on the Host yet. 

"The width of the built-in FIFO must be less than or equal to 1024." is talking about how many bits per data point (element). So you can, in theory, store a cluster of 16 64-bit values each cycle into the (Target-Scoped) FIFOs.

Hope this helps!