FIFO between FPGA and RT (Compact RIO)

[ZoltanMTS]

Hi,

I have inherited two Labview codes for Compact RIO. They have quiet similar structure, with some differences. My problem is with the FIFO between FPGA and RT, which passes an array. The actual code is different, as one has no CAN messages and another has 2 CAN channels. In both cases, I had to change the size of the array – it worked with the one without CAN, but it does not work with the one with CAN.

The one without CAN is like in attachment 1 (FIFO_Mod4.png).

The input to the For loop is a 1-D array of 107 FXP <+/- 26,5>, which is getting through.

Another one with CAN is like in attachment 2 (FIFO_Mod8.png)

It has two CAN channels and the third element of the array is a bunch of analog and digital signals. The input to the For loop is a 1-D array of 290 FXP <+/- 26,5>, but only 160 FXP is getting through, which is the original size of the array.

In both cases, auto-indexing is enabled.

Questions:

1. May the different structures cause different behaviors?
2. Are there any other places in the code, where the size of the array can be influenced (defined or restricted) for the second case?

Thanks.

Regards,

Zoltan

[crossrulz]

Go to your project and open up the settings for this FIFO.  Make sure it is set to be large enough to handle all of the data.

[ZoltanMTS]

Thanks, but I have doubled that from 1024 to 2048.