FIFO issue in continuous streaming data from host to target FPGA

[tintin_99]

Thanks Bob and Nathand for your help. You are completely right Bob. 

This is what I want I want to do

From the host side, I have to transfer output for my IOs for each cycle, plus timing parameters on how to generate a specific pattern for each cycle.

The VI below is a down counter. Based on the divider value , it create a cycle clock and a down counter value. If the divider is 10 then it means it counts from 9 to 0 and when it reached to 10, the Boolean output becomes true ( to create cycle clock ) and teh counter also resets to 9. As you can see, this means each cycle clock is generated with 10 FPGA clock ticks

The generated counter then will be used to flip flop or high-low the IOs based on timing values. For example , when counter is 7 "sda" should go high. when counter is 5 sda should flip flop and when counter is 1 sda should go low. This way I can create a pattern for 1 cycle of sda signal

As you can see, the down counter and start button triggers everything. The code below , disables the start button after reading all the cycles . This stops the down counter.

FIFO also should read data in cycle_clk speed and not FPGA speed. When cycle_clk is enabled I should read 1 element for the DMA FIFO and pass it for processing. As I mentioned above, the element is U32 integer which contains the output and timings for each signal.

The whole logic works properly. It works exactly as expected. But I have 2 problems

1. I should be able to generate a 10MHz cycle clock and with divider of 10 , this means , have to compile the FPGA at 100MHz. But I can't compile it higher than 60MHz and at 100MHz I get timing violations .

2. When I transfer my big array ( 2 million is the array size ) from host DMA FIFO to target DMA FIFO the program works properly. I never get Read FIFO issue and the pattern runs and executes properly, But when I pass the short array ( 65000 array size ) then I see all these FIFO issues.

So it would be great if you could help me remove extra stuff to be able to run it 100MHz and also the fifo issue. I changed one thing today and now I see the short array works and the long array doesn't

I added the below check to make sure there is an element in the FIFO. If there is no element then down counter stops counting ( attached )

I attached the code as well. The name of the FPGA file is untitled short and host is the host VI. Sorry if the code is not clean

[nathand]

I'm still on LabVIEW 2012 here so I can't open your code, although from your screenshots it looks like it's more complicated than necessary, and it would definitely help to clean it up. Again, no need to compare a value to False - that's just a boolean NOT. However, since you're running that value into a Select, swap the T and F inputs and wire the boolean directly.

Personally I'd probably structure this differently. One option would be to generate a much larger array on the host side, containing the desired value for each output on each clock cycle (if the value doesn't change, the same value is repeated). Then the FPGA code becomes as simple as read from the FIFO, set the outputs, at a fixed clock rate (or maybe with a variable divider). If you can't get the FPGA to compile at your desired clock rate that way, try pipelining, where you read from the DMA FIFO directly into a shift register, then use that shift register value on the next cycle in parallel with the next DMA FIFO read.

[tintin_99]

I still would prefer to make the digital pattern in FPGA , but to test your suggestion I made the whole array in host. Result is a constant array that can be presented in target Vi either using FIFO or by indexing from the constant array

I started with indexing from constant array . It works as expected in 60MHz but again I get timing violation when I compile at 100MHz. I can't really make it simpler. I saved the VI in 2012 format.Coudl you please check it to see what else can be done to eb able to compile it at 100MHz. It is off by 0.5ns while teh duty cycle is 10ns

[nathand]

There's always a limit to how fast a loop you can compile on an FPGA. What makes you think that it should be possible to run your code that fast? Have you successfully compiled any code at that clock rate? Can you provide a screenshot showing where the timing error is? It's possible that the combination of Set Output Data and Set Output Enable can't be made to run in a 100Mhz clock. There's not much other logic there. The one thing I can think of to try is move the constant array into a memory block (storing a constant array that large will waste a lot of FPGA space, and you can initialize the memory block to your array values). You'll need to add a shift register, read the memory directly into that shift register, and on the following iteration use the shift register value to set your outputs while reading the next memory address. I don't know if that will let you compile it at 100mhz, though.

[Bob_Schor]

I must be missing something (like a screw in my brain).  You are able (by adding in duplicate points) to generate data for the FPGA to output your waveform at 100MHz, but the FPGA can only run at 60MHz, so you get errors.  Why not give it "every other point", and run the FPGA at 50 MHz?  [I don't have an cRIO here, so I can't open your RT code -- forgive me if this a completely stupid question.]

Bob Schor

[tintin_99]

Hi nathand.

I replaced the constant array with DMA FIFO Read and now I can compile it at 100MHz but I see the lines are not toggling I attached the VI. Could you please quickly check

[tintin_99]

Bob,

To be able to make the digital pattern , I need to run the FPGA at 100MHz. It works at 60MHz but it is not fast enough for my application

[nathand]

There's no need for "Get Number of Elements to Read." Use the timeout output from the FIFO Read instead. If it's true, you didn't read an  element. This also avoids the risk that elements become available in the FIFO between the time that you read and the time that you get the number of elements.

I don't see any obvious reason that code wouldn't work, though. Does it work in simulation, when you set the FPGA to execute on the development computer?

[tintin_99]

Well, I see the line are toggling but seems like when the FIFO time out becomes true , it stays true after that or at least for a considerable amount of time and that time kills the communication. I even tested at 80MHz and I get the same response.This is my simple host code. Seems like Host FIFO can't really keep up with the FPGA . Can it be a hardware limitation? My FPGA card is PXI 7813R and the backplane is PXI not PXIe 

[tintin_99]

It doesn't work even with  10MHz FPGA clock. Again ,as soon as the toggling starts and after few cycle_clk full periods it goes in to a weird state and everything stops  and I think it is related to the  transfer between host and target