FIFO size DMA

[lightmiddle]

Hi :

   I just read about the "Using DMA FIFO to Develop High-Speed Data Acquistion Applications for Reconfigurable I/O Devices"

 It said "This allows the FPGA to use the host RAM as if it were its own".

  I am using Labview for windows and PXI 7833R card. The 7833R card has a 190k RAM. Since my host has 512M memory.

 So can I creat a memory block or FIFO with size of 10M ? And can I read the FIFO at a fixed rate like 8M?

I wanna send the data from FIFO to a device at fixed frequency (4M or 8M Hz), is it possible?

Thanks.

[Prashanth]

As of LabVIEW FPGA 8.0, the DMA FIFO data transfer is only one way - from FPGA target to the host controller. Future versions of the FPGA module will include DMA data transfer capabilities in both directions. LabVIEW FPGA 7.1 could not use DMA for data transfer, and the maximum data transfer rate from the FPGA to the host controller was about 1M. With LabVIEW FPGA 8.0, the data transfer is now atleast 20x faster.

There are two parts to the DMA FIFO: a part that exists on the FPGA target and another that exists on the host computer. In the FPGA target, when you create the FIFO and specify the depth in the FIFO configuration window, you are specifying the depth of the FIFO on the FPGA hardware. To specify the depth of the FIFO on the host controller, set the 'Depth' attribute in the invoke node in the FPGA interface vi. The tutorial you referenced in your post shows a good example of this concept.

The data transfer rate from the FPGA to the host is determined by the rate at which you write to your FIFO.

Hope this helps!
Regards,
Prashanth

[lightmiddle]

Thanks Prashanth

Then what is the fastest way to stream data into FPGA ? What is the transfer rate?

Right now I am using the memory onboard to save the data from host to FPGA. However the onboard memory is only 190K bytes. Is there any way to stream very large amount of data into FPGA very fast one time?

Thanks again. 

[Doug M]

lightmidd..

Yes, unfortunately currently DMA transfer is only one-directional from the FPGA to the host, so there isn't a faster way to transfer from the host to the FPGA, and like you mentioned you are limited by the size of the memory on the FPGA.  The fastest way to transfer from the host to the FPGA is going to be to transfer in 32 bit chunks per loop iteration, probably using some sort of handshaking scheme.  One idea would be to have a two-frame sequence structure in the loop on both the host and FPGA VIs, the host waiting for a send flag from the FPGA and then sending 32 bits of data, and the FPGA VI reading from this control and toggling the send flag.