FPGA 64-bit Tick counter

[MarcoMauri]

I've a (simple) question about the 64 bit tick counter example that can be downloaded here.

I wonder why the Tick count engine is so "complex":

 

Maybe simply adding two 64-bit numbers (the tick count value plus 1, both U64) is taking too much time to fit in the SCTL...

Thank you in advance!

Marco

[Chuck_81]

Hi Marco, 

the reasons why the example has been programmed this way could be more than one:

• Working in parallel with two U32s instead of a single U64 could increase the logic speed
• The example has been developed in LV FPGA 8.5.1; that versions did not have saturation monitoring features for add/sub/multiply functions, so working with 64 bits required to split operations in several sub-operation of 32 bits
• Support for 64 bits was newly introduced in LV 8.5.1 and there would have been some performance issue

Anyway, if you work in LV 8.6 and later you can easily use 64 bit registers, as shown in the attached VI.

Hope this helps,

Fabio 

Message Edited by Chuck_81 on 06-16-2010 09:56 AM

[MarcoMauri]

Thank you for your reply!

In any case I've added an idea in the FPGA Idea Exchange Forum, requesting 

a built-in 64 tick counter, that I'm sure is quite useful.

If anyone want to support this, the post is 64 bit FPGA tick-counter

Regards,

Marco