FPGA Compile Error: Cannot find input file "toplevel_gen_map.ncd

[rex1030]

I am running 8.6 on a cRIO 9104 backplane with a cRIO 9012 RT controller. I keep getting this compile error when I try to compile my FPGA code. I have never seen anything like it before and really need some help. It compiles for four hours then throws this error. I have tried to compile twice. Can anyone help?

 This is the last page of the compile print out if that helps:

#----------------------------------------------#
# Starting program post_map_trce
# trce -e 3 -xml toplevel_gen_map.twx -intstyle xflow toplevel_gen_map.ncd
toplevel_gen.pcf
#----------------------------------------------#
ERROR:TimingToolsC:14 - Unable to access design file: toplevel_gen_map.ncd



#----------------------------------------------#
# Starting program par
# par -w -ol std -intstyle xflow toplevel_gen_map.ncd toplevel_gen.ncd
toplevel_gen.pcf
#----------------------------------------------#


ERROR:Par:73 - Cannot find Input file "toplevel_gen_map.ncd".  Please verify that your paths and permissions are
   properly set for this file.
ERROR:Xflow - Program par returned error code 21. Aborting flow execution...

""

Please help me because I need this thing to work. I have attached the fpga file I am compiling.

[muks]

IIs it because of version conflict?

[Eli_S]

Hi Rex1030,

I am working with you on this issue through the SR you created. I will post the solution here once we resolve it so everyone can have access to it.