FPGA Compile error, xst:762

[RichE]

When trying to compile my FPGA I get the following error,

_________________________________________________

Analyzing Entity <flatSeq_153e78c_1738_frame0_000159b4> (Architecture <vhdl_labview>).
ERROR:Xst:762 - D:/NIFPGA11/srvrTmp/LOCALH~1/CARDIF~1/rvi_cardiff_racing_fpga.vhd line 1815: No default binding for component: <flatSeq_153e78c_1738_frame0_00015054>. Port <res_80000000> does not match.
-->

Total memory usage is 157204 kilobytes

ERROR:Xflow - Program xst returned error code 6. Aborting flow execution...

__________________________________________________

I have recently updated my NI RIO driver to 1.3.1 and I have made sure that I have no unconnected terminals in my sub vi's.

Please could someone help, I have run out of ideas.

Richard Elliott

[RichE]

I have now modified my code and it compiles ok. I am still not any wiser as to why it didn't work before.

Richard Elliott