FPGA DAQ and triggered motion control

[ajfaul]

I currently have a setup using Labview 8.5 on a host PC and using a PC as RT target with an NI 7830R FPGA module for DAQ and a NI7350 motion control module.  I am reading three analog inputs (call them AoP, AoF and LvP) in the FPGA and setting a trigger based on a threshold level associated with the (LvP) input.  Once the trigger is detected, AoP and AoF data must be collected for a user defined time (1), averaged and used in a PI controller to calculate the cw position of the motor.  When the next trigger is detected, the motor must move cw for a user defined time (2) to the position calculated and the PI controller must calculate the next position.  After the user defined time (2), the motor must move ccw for a user defined (3) time and then repeat the cw and ccw motions. 

I completed the FPGA and host vi's, but I have some problems finalizing the project and will appreciate any help.

1. The trigger is detected and the motor motion occurs as required, but it is not always synchronized with the triggers.  How can I fix that?

2. Do I need to use a FIFO to get the data from the FPGA to the host, since the FPGA is running faster than the host?

3. Am I calculating the averages for the two inputs correctly?

4. I am not sure how to implement the user defined time (1).  I have tried to use a case structure and flat sequence, but that did not work.

5. Is there a way to make the host vi run faster?  At the moment it seems that it takes about 390ms to complete.

The FPGA and host vi's are attached.  I will appreciate any and all suggestions, comments and help.

Andre

[Andrew_E]

Hi ajfaul,

I am going to answer the easiest one first.

2) Yes, you should use a FIFO

1) Could you clarify what you mean by "not always synchronized with  the triggers"? Your trigger is on your host, on your pc, so it would not be Real-Time, plus it appears to be "user defined"

3) Could you also clarify "calculating the averages correctly", i am assuming its just not Sum of Samples / # of Samples Taken but something else?

4) for user defined time(1) , is that millisecond to wait before eject, AI Loop time, or Millisecond multiple? Or have you not implemented it yet. It seems like you would use a wait function, with a user control input. Count how many ticks you have been aquiring data, compare that to the user defined time, and use local variables to stop the data aquisitiion.

5) The host vi is software timing, so the only way to "make it faster" would be to reduce the time you were set the wait functions in your loop.

[ajfaul]

Hi Andrew,

Thanks for the feedback.

1) My trigger is provided by the "over threshold" output from the SCTL in my FPGA vi.  My host vi and FPGA vi are part of a RT project that runs on the RT target PC, so setting the threshold level and reading the "over threshold" output from the FPGA should then occur in RT, or am I missing something?  Setting the threshold level is user defined in the host vi, but detection of threshold level crossing occurs in the FPGA vi.  What I am seeing when I run the host vi, is that the trigger is detected and correct cw and ccw motion occurs for about four cycles, after which the motion pauses for a couple of seconds and then continues as before.

3) In my host vi, I use the "mean ptbypt.vi" to calculate the averages of AoP and AoF during the time that the threshold is exceeded and use this as process variable input for the PID controller.  I am not sure if this is the best way of calculating the averages of these signals.

4)  The user defined time(1) has not been implemented yet. I will try to use your recommendations.

5)  Even when I set the "fill time" and "eject time" to 200ms and the "ms to wait before eject" to 1ms, the loop takes 390ms to complete, so it seems that there is timing overhead that can be reduced, but I am not sure where that is.

2)  I have tried to transfer the data from the FPGA to the host using a FIFO, but I am having a bit of a problem reading the data on the host.  All the examples that I could find put all the data into one array for display on a graph.  I need to read each AI individually and I have to make sure that I am just reading that AI and not some data from another AI.  Can you point me to any examples or inlcude a sample vi to show me how to do that?

Thanks again for taking time to respond to my problem.

Regards

Andre

[Andrew_E]

Hi Ajfaul,

1) Could you refine what you mean by "continues as before", is this start for 4 cycles and stop for a few seconds, cyclical? It could be that your system is working correctly, and that the code is telling it to wait for that given period of time.

3) I looked at the mean ptbypt.vi and that seems to work for your application.

2) I would suggest you use DMA FIFO to allocate memory in both your host PC and in your FPGA to do the task that you wish to be done. Here is a link that talks about DMA FIFO's and how to implement them. I would suggest walking through the implementation and putting that into both your fpga and host vi's.

Regards,

[ajfaul]

Hi Andrew,

1) Yes, it is cyclical.

2) I will implement the FIFO's as you recommend.

Thanks for the help.  I will try out your suggestions.

Andre

[ajfaul]

Andrew,

I have implemented the FIFO as you suggested, as shown in the attached pictures, but still have problems reading the data.  I will appreciate your comments on the following:

1)  I have set the depth of the FIFO on the FPGA to 4095, but I still get the timeout going active when running the FPGA at 100us, the host vi at 30ms and setting the number of elements to read to 10000.

2)  How do I determine the optimum setting for the number of elements to read?

3) When I set the host vi loop rate lower to say 10ms, it still takes more than 200ms to complete the loop.  Why is this?

I will appreciate your help.

Thanks

Andre

[Eli_S]

Hi,

I assume you are getting the timeout on the host side, correct? If this is the case, there are several ways you can fix this. The timeout means that you are trying to read elements when the FIFO is empty for a time longer than your timeout setting. To fix this, you can either decrease the samples to read, decrease the speed of the Reading loop (on the host), or increase the speed of the FPGA VI (FIFO writes) to make more samples available.

There is no optimal way to determine all these settings, they all depend on your application and on the nature of your code.

[ajfaul]

Eli,

Thanks for the response.  No, I am reading the timeout on the FPGA side, which as I understand it, means that the FIFO gets filled up and that I am not reading the data fast enough.  As I mentioned before, even when I set the loop on the host to run at 30ms, it takes between 200 and 300ms to complete.  I cannot understand why it takes so long.

Thanks

Andre

[Andrew_E]

Hi Andre,

You should create the FIFO in a seperate loop from your main code, and communicate the data to it via a queue. That way your data output won't be slowed by the main body of your code.

Regards,

[ajfaul]

Hi Andrew,

It makes sense putting the FIFO in a separate loop, I will try that.  I do not quite understand what you mean with "communicate the data to it via a queue".  Can you please explain that a bit more?

Thanks

Andre