FPGA:DMA FIFO delays other modlues

[maxsun]

Dear All,

Iam developing a testing system..... I am using NI 9225,9239,9205,9264,9425,9476,9213,9233.

I Have attached the basic code for reading from these modules. Iam using two DMA FIFOs for 9225 and 9239.

Problem:
when i use DMA FIFO , the other modules values acquisition is very slow. Also the DMA FIFO output shows correct values when i start the code.... but after some time it displays wrong values....

I want to read data at 1KS/s..... I know that i am making some where mistake...

Could somebody please tell me where i am doing wrong...

[andre.buurman@carya]

I think it better to separate the two DMA FIFO calls into two loops and have them put there data in a RT FIFO, and have those RT FIFO's handled by a consumer loop. Thus creating 2 producer loops (one for each DMA FIFO) and 1 consumer loop that handles the acquired data.

For reading the DMA FIFO, I would recommend not to use a time out value greater than 1 ms, it eats you CPU (at least on a RT target it does).

Use two consecutive calls with a timeout value of 0 ms. Have the first call ask for 0 elements, it will return the remaining elements, and when the remaing elements is equal to or greater than a set number of samples, retrieve the set number of samples with the second call. Only add samples to the RT FIFO when the second call is executed and returs data.

Message Edited by andre.buurman@carya on 03-10-2010 04:18 PM

[Kosta]

The FPGA VI contains a couple of FIFO Write nodes with 0 wired to Timeout input, and the Timed Out? output not monitored.  These Write nodes attempt to write into the DMA FIFOs.  If the host is not keeping up with the data being written into the DMA FIFOs, these FIFOs will fill up, and writes will not add anything into the FIFO until reads make more room.  The FPGA VI is not monitoring for this error condition. 

To properly monitor Timed Out? outputs, you should latch the value and then wire it to an indicator, like this:

Monitoring these outputs (and a true value means that the reads have at some point failed to keep up with the writes) should help you figure out how big the FIFOs need to be and how to go about reading them on the host side.