FPGA DSP fixed-point

[St3ve]

Hi,

I am looking at using the DSP48 slices found on the (some) FPGA target. The data input type is FXP but from the Xilinx documentation it seems the inputs are actually 2's complement integer, is this the case?

Thanks,

Steve.

[Rob_Ward]

Hey Steve

Thats a really good observation!  As a physicist by training I have always found these things interesting so thanks for raising this issue.

It woud appear that you are certainly correct.  According to the Xilinx doccumentation "the DSP48E1 multiplier has asymmetric inputs and accepts 18-bit twos complement operand and a 25-bit twos complement operand". 

I wanted to find out more about this as to why this is the case so did a bit more research.  It would appear that calculators are faster at shifting than they are at adding bits, so there are advantages at inputting numbers as a twos complement in for example Booth's Multiplication Algorithm.  I believe that in effect; it is quicker for the processor to calculate (-3 x -4) x (-1) = -12 than it is to calculate (3x-4) = -12 and since you are working on FPGA I could see how this could improve performance of the processor.

I hope this helps.

Regards,

[JLewis]

Hi Steve,

In general, Xilinx doesn't specify FXP types because the underlying hardware is the same in either case. The FXP type presented by LabVIEW is just an abstraction that handles implicit scaling for you to allow viewing the data in a more useful format. To use the DSP48E node, treat the inputs and outputs as FXP data like you would for any other operations.

As Rob alluded to, the 2s complement (signed) part is a property of the hardware multiplier itself, and is important because that means the width limits for unsigned data in a single DSP48 block are actually 17x24 instead of the 18x25 that we normally talk about for signed inputs.

Jim