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FPGA FXP Discrete Delay

Is there any way to zero out the FXP Discrete Delay array in one cycle of a single cycle loop?
 
Thanks!
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Message 1 of 7
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Hi tartan5,

I have been reading your post and I was hoping you could give us a little more information about your application. I'm assuming you are using the Discrete Delay.vi inside a single-cycle timed loop but can you tell us a bit more about what you are trying to accomplish? Maybe even posting a screenshot of what you have right now and a description of what you are trying to do would really help us out.

Thanks,

 

Carla

National Instruments
Applications Engineer
Message 2 of 7
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Hi Carla,
 
I was working on an 2^n point moving average.  Essentially, I add the new datapoint to the sum, subtract off the oldest datapoint, then multiply by 2^-n.  One of the issues this code has is that if the VI is reset, the old data in the buffer is still subtracted out, giving incorrect results.  I am thinking of getting around this by implementing a counter, if the counter is < 2^N then I ignore the data coming out of the buffer (don't subtract it)......When the counter hits 2^n then I can set a DATA VALID flag........
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Ok, so here is my work around.  Essentially if the vi is reset I ignore the data from the buffer until it has loaded 2^n samples, then the Sample Valid goes high, at which time the vi is performing a moving window average.  Note that changes to N are blocked until a reset signal occurs.
 
Anyone see any flaws, or see a simpler way of doing it?
 
Thanks!
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Just a note, to open the VI you will need 8.5, and the additional "Fixed-Point Math Library for LabVIEW FPGA"

Thanks again....

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Hi tartan5,
 
I think that you are on the right track. That was the first thought that I had. I would go ahead and try to implement that and if you have any trouble, let us know and we can help you out. Have a great weekend!
 
 
National Instruments
Applications Engineer
Message 6 of 7
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Is not better to subtract old sample from "accumulator" before you add new sample to accumulator? This could protect against overflow. Another think is that we design accumulator size big enough to not overflow.

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