FPGA Loop Timer Runs Unchecked When Executing on Development Computer

[Wes1s]

Hello forum,

I am developing FPGA code, and I am running and debugging with the Execute VI on > Development Computer with Simulated I/O option. However, I have noticed that my Loop Timer VIs do not seem to be timing my loops. The loops run unchecked as if they have no timing in them at all. This is how I implement it:

1. I place the Loop Timer VIs within a Conditional Disable Structure with FPGA_EMULATION==TRUE.
2. That Conditional Disable Structure is in the first frame of a Flat Sequence Structure.
3. This is all in a While Loop

I can create a blank VI from a blank project and have the same results. My understanding is that when a Loop Timer VI executes on the Development Computer, it automatically rounds to ms since Windows only has 1 ms resolution. But even if I choose mSec as the Counter units and wire in 1000 or 10000 I get the same results. From using the blank VI and 10000 mSec wired in, I know that my code is not taking longer than the Timer duration, so it should not return immediately.

I feel like I am just missing something simple, but have not been able to find any reference to this issue in the forums or through searching elsewhere.

Thank you for your help,

W

[ToeCutter]

Isn't it doing what you specified- i.e. timer disabled in emulation mode? Or am I missing something?

[T-REX$]

I bet you're running LabVIEW 2013?

If so, there is a "new" concept of simulated time that was introduced to improve desktop simulation fidelity. Check out the "What is Simulated Time" section of this Using the LabVIEW FPGA Desktop Execution Node white-paper, and the LabVIEW 2013 FPGA module help topic for an explanation. I know there is some hand-waviness around it, but it's an important tool that allows the new Desktop Execution Node and Waveform Sampling Probe features to exist.

[Wes1s]

Hi T-REX$,

I am in fact using LabVIEW 2013. I appreciate the links. But is this seriously the only way? This is WAY more complicated than just dropping a Loop Timer in my Host VI and verifying the behavior of my code. The time/cost of rewriting my host code instead of just using the Loop Timer makes me feel like I should just go back to LabVIEW 2012.

[Catherine-B]

Hi Wes1s, 

You can still run your code using simulated I/O without using a Desktop Execution Node. This allows you to make sure the logic of your code is correct. In earlier versions of LabVIEW, simulated time more closely resembled wall clock time but it was not strictly the same as desktop computers are not capable of the speeds an FPGA is. The article below discusses the various options for debugging FPGA code. As shown in the table, running the FPGA in simulation mode only verifies the timing of code contained in a single-cycle timed loop. To verify all timing, you need to run the code on the FPGA or use a 3^rd party simulator.

https://www.ni.com/en/support/documentation/supplemental/21/testing-and-debugging-labview-fpga-code....

Best,