FPGA Outputs Do Not Work in Loop With Fast Derived Clock

[wtribley]

Using a PXI 7813R RIO board with a built-in NI controller in a PXI chassis (the NI way!). I need a 10mHz reference clock. So, to be lazy I tried using a derived 20mHz clock with a timed loop, inverter and shift register, no joy: the output was tri-stated. To verify I wired two outputs, making sure one of them was not blown. Then I used a timed loop with the default 40mHz clock and a more complex divide-by-4 arrangement, viola: it works. Why?

Thanks for any input,

Bill 

[Ruhmann · Accepted solution]

I looked at your PDF and tried to recreate your application in LabVIEW 2009 and the 20 MHz single cycle timed loop worked just fine.  I physically wired the output DIO to another DIO which I read in an 80 MHz loop and measured a 10 MHz clock.

What version of LabVIEW and NI-RIO are you using?  If you right-click on the DIO in the project and go to properties, are the data and enable both set to "Never Arbitrate" and have 1 synchronizing register?  I don't think either of those settings will matter, but it might be one of the differences between our applications.   Are you sure the 20 MHz loop is executing?  (The DIO will be tristated until the IO node executes.)  What did you derive the 20 MHz clock from?  Can you post your project and VI?

[JMota]

An easy way to ensure this

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Ruhmann wrote:

Are you sure the 20 MHz loop is executing?  (The DIO will be tristated until the IO node executes.) 

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is to create an indicator out of the loop index and see if that numeric indicator gets updated on the front panel (vs staying at zero).

[wtribley]

Thanks for the replies. I discovered an interesting property of these high-frequency outputs: they can have a significant 60Hz component because they exhibit a higher impedance while switching. If I turn the scope horizontal to something close to the 10mHz range it appears, otherwise it looks like hum. So, it was working all along.