FPGA Parallel IO Speed

[Eldrich]

Hi,

I'm trying to read and write to several FPGA analog IO's in parallel.

I'm using a cRIO 9076 and a NI9467 & NI9205 for the outputs and inputs respectively.

The problem i'm facing is that i need to sample each of the inputs and write to all the outputs every 50usec.

With the hardware that i'm using now, the fastest i can achieve is about 120usec.

Also, to simplify the coding process, i'm using FIFO's for data transfer between the RT host VI and the FPGA VI (instead of interrupts). I'm also RT VI directly on a host computer (i don't have another VI to communicate with the RT VI).

Could any of these be the problem?

I can upload the code if anyone would want to take a look.

Thanks!

[srm@viewpointusa.com]

9467 is the GPS module  how are you using that in your application?

Also, how many channels of the 9205 are you using?  that module is multiplexed and has a maximum aggregate rate that will affect your per channel rate.

[Eldrich]

My bad.

I'm using an analog output module. It's got 16 analog outputs. I can't remember the number right now, but i'll get back to you on that.

There's also the matter that i don't have a VI running on my computer to handle data communication. The VI i'm running is the RT VI, which calls the FPGA VI, that's it. Could this possibly be the problem why my data transfer rates are limited?

The minimum loop rate that i can achieve with 5 input channels is about 120msec, which is much higher than what i need.

Thanks for the reply!

[srm@viewpointusa.com]

what is your RT code doing?  can it be performed on the FPGA?  you will not be able to get 20 kHz input/process/output with the approach that you are using.  if you do all of the work on the FPGA, it will be possible, depending on what processing you need to do.

[Eldrich]

My RT code reads data from the FPGA's, analyses and displays it on a graph.

There is also an FFT and filter.

I was just wondering if it really is sensible to run the application as it. What i mean is that there is no VI on my computer, i'm direclty running and interacting with the RT VI.

The RT code can be run on the FPGA and this is exactly what i tried to do with one of the NI examples (four parallel controllers on the FPGA, with controls on a workstation).

Cheers!

[Eldrich]

The code is attached if you would rather look at it than at my attempts to explain it!