FPGA Parallel while loops not independent?

[Riggy]

I'm creating a basic test code for my CompactRIO 9074.In one test, I created a very simple while loop for acquiring a single data point from an NI-9205 analogue input module at 1 kHz. I then wrote a second test program which calculates the period of a TTL signal on input 0 of a NI-9401 digital IO module. This runs at the clock speed of 40MHz and returns the period in clock ticks.

I get unexpected behaviour though if I combine both while loops together into one test code. The while loops are independent, yet the second loop gets slowed down

This is a screen shot of the FPGA code with both while loops - the top while loop is from the analogue input test program, the second while loop is from the TTL period test program. The output loop period (ticks) allow me to identify that the loop rate has dropped from 1 tick per iteration (40 MHz) to about 24 ticks per iteration (1.66 MHz). Can anyone tell me why the second while loop is slowed when the first while loop is added to the code? Aren't these mutually exclusive and therefore independent?

Thanks all for any advice.

[falkpl]

Too early to think about FPGA code on a monday morning but it might have to do with the local and the arbitaration for this local.  Are the 2 loops really independant if you have a shared local (I cant remember). 

[Mark_SAI]

What happens if you make the 2nd loop a single cycle timed loop?

( http://zone.ni.com/reference/en-XX/help/371599E-01/lvfpgaconcepts/using_sctl_optimize_fpga/ )

[Riggy]

Thanks all, I'll try removing the shared variable and using a timed loop, and let you know what happens

(sorry for the late response, I only work Monday and Friday!)